Daniel Mathiot

A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections

High-speed cameras use the interesting performances of CMOS imagers that offer advantages in on-chip functionalities, system power reduction, cost, and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, a new imager called FAMOSI 2, which implements an electronic shutter and analog accumulation capabilities inside the pixel, is presented. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in repetitive mode for low light power and in single shot mode for higher light power. This repetitive mode utilizes an analog accumulation to improve the sensitivity of the system with a standard n-well/psub photodiode. The characterization has been realized in single shot mode to optimize the accumulation mode. The prototype has been fabricated in the Austriamicrosystems 0.35-mum CMOS process. The chip is composed of 64 columns times 64 rows of pixels. The pixels have a size of 20 mum times 20 mum and a fill factor of 47%

Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology

The conventional streak camera (CSC) is an optoelectronic instrument that captures the spatial distribution as a function of time of an ultra high-speed luminous phenomenon with picosecond temporal resolution and a typical spatial resolution of several tens of micrometers. This paper presents two tubeless streak camera architectures called MISC (matrix integrated streak camera) and VISC (vector integrated streak camera), which replicate the functionality of a CSC on a single CMOS chip. The MISC structure consists of a lens, which spreads the photon flux on the surface of a specific pixel array-based (Bi)CMOS sensor. The VISC architecture is based on a sensor featuring a single column of photodetectors, where each element is coupled to a front-end and a multi-sampling and storage unit. In this case the optical objective used in front of the sensor focuses the luminous event on the several tens of micrometers wide photosensitive column. For both architectures, the spatial resolution is linked to the size of the photodetector and the temporal resolution is determined by the bandwidths of the photodetectors and the signal conditioning electronics. The capture of a 6 ns full width at half maximum 532 nm laser pulse is reported for two generations of MISC and a first generation of VISC.

Kinetics of arsenic segregation at grain boundaries in polycrystalline silicon

By comparison between chemically and electrically active As concentrations in polycrystalline silicon thin films with a well-stabilized grain size, the equilibrium segregation coefficient relating the grain boundary and the Si grain is experimentally obtained in the 750 - C temperature range. Moreover, by using isothermal short anneals, it has been possible to study the kinetics of the segregation phenomena. It is found that the time constant corresponding to the achievement of the equilibrium state strongly depends on the annealing temperature. The kinetics coefficients controlling the rates of exchange between the grains and the grain boundaries have been extracted on the basis of a simple kinetics model. The technological relevance of these results for the doping control of the polycrystalline silicon layers is pointed out.

Collection Efficiency of Noble Metallic Contaminants on Si Wafers with HF-Aqua Regia Mixtures for VPD-DC ICPMS Analysis

of several new materials in clean rooms, the monitoring of trace metallic contamination is a real and present need. It is well known [1][2][3] that these impurities are detrimental to the efficiency of the microelectronics devices: they could cause crystal defects, act as electron traps, degrade minority carrier lifetime or increase the leakage current. Concerning the noble metallic contaminants (Au, Pt, Ir, Ru, Ag and Pd), now used in microelectronics to improve devices performances, their surface contamination control at low level (< 1010 at.cm-2) remains a great challenge.

Architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology

This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a Conventional Streak Camera (CSC), coupled to an amplifier stage and an analog sampling and storage unit. For both architectures, depending on the on-chip processing of the photocharges, appropriate signal reconstruction techniques are required in order to restore the luminous signal shape. A novel single vector ISC front-end architecture with an asynchronous photodiode reset scheme is presented. Algorithms allowing the luminous event reconstruction are proposed and validated through simulations for all the ISCs considered.

Integration of InGaAs/InP structure above ROIC-CMOS for SWIR imaging

Nowadays short wavelength infrared (SWIR) imaging based on InP/InGaAs photo-diodes is quite popular for uncooled camera. The state of the art technology is a double layer planar heterointerface focal plane array [1]. But, it remains expensive and only used for defense and scientific applications. Its cost comes essentially from the individually hybridization of photo-diodes array with read-out circuit, by the mean of an indium-bumps flip-chip process. We suggest an alternative method for hybridization, in order to lowering the cost and providing a sustainable process to decrease the pixel pitch, and also increase the possible format. It consists in a direct integration of InP/InGaAs/InP structure above a finished read-out circuit (with CMOS technology) and circular diode architecture.

Surface analysis of InP and InGaAs after low temperature diffusion of Zinc

In order to develop III–V based devices integrated directly above post-processed silicon wafers, low temperature diffusion of zinc in n-type InP and InGaAs is studied at compatible temperatures, below 425 oC. We particularly focus on the resulting surface degradation. Efficient Zn diffusion is obtained for InGaAs samples, where the surface remains mirror-like after thermal treatment. Conversely, no significant diffusion occurs in InP where the surface is deeply deteriorated. The stability study for InP under thermal annealing in various ambients allows us to rule out thermal dephosphorization as the main cause of the surface degradation. On the basis of experimental observations and thermodynamic considerations, it is suggested that InP degradation is linked to the direct interaction of Zn and P, inducing the formation of parasitic Zn x P2 alloys, which also hinders the efficient diffusion of Zn into the InP substrate.

Spectroscopic Studies of Iron and Chromium in Germanium

We report on the electronic properties of Fe and Cr in n-type germanium using conventional and Laplace DLTS techniques, which in the case of Schottky barriers, are restricted to levels located in the upper half of the band gap. In this work we present extensive DLTS and Laplace DLTS results, re-examining various basic properties of Fe and Cr in n-type Ge samples. In addition our analysis bring new insights into the microscopic behavior of these two chemical species such as their interactions with hydrogen present as an unwanted contaminant, giving rise to the generation of other related levels in the band gap.