Daniel P. O'Connor

Modeling and simulation of core switching noise for ASICs

This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.

Effect of organic package core via pitch reduction on power distribution performance

Advances in CMOS technology continue to provide increased circuit density and performance at a lower cost. Die size and cost can be further reduced for I/O limited applications by shrinking the area array flip-chip (C4) pad pitch. These advances continue to drive package ground rule improvements to efficiently distribute signal and power while reducing cost. One such groundrule for organic build-up packages is the core via pitch. Core via pitch reduction can significantly improve the package power distribution and signal escape. This paper presents the package design tradeoffs for core via pitch reduction to support a 90nm 9.3mm ASIC die using a 150/spl mu/m full area array C4 pitch. The impact of core via pitch on power distribution performance, wireability, and cost will be presented, including electrical modeling and simulation results. Design trade-offs to optimize both the chip and package are presented, including die C4 pad pitch and depth versus module cost and performance.

Modeling and simulation of core switching noise on a package and board

This paper presents simulation and analysis of core switching noise on a CMOS test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.

Electrical modeling and characterization of packaging solutions utilizing lead-free second level interconnects

This paper presents measured and modeled results of two novel lead-free interconnect solutions. A surface mounted Copper Column Grid Array (CuCGA) and a demountable Spring Land Grid Array (SLGA) will be characterized and compared to the standard Column Grid Array (CGA). The geometries and materials required for reliable connections often compete with the ones required for adequate electrical performance. To characterize the electrical performance differences, several IBM ASIC menu alumina packages were built, vatying the physical propelties of the second level interconnects for both the CuCGA and SLGA technologies. The corresponding parts were modeled and measured for loop inductance and DC resistance of the power distribution system. Excellent model to hardware correlation was achieved, and clear candidates are recommended for equivalent or better performance compared to standard CGA interconnects.

Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)

For the first time, compact physical models are derived in this work that enable quick package- and chip-scale calculations of the power supply noise and incorporate the distributed natures of on-chip power/ground grids and package-level power/ground planes. Designers can use these models to perform chip/package co-design for power distribution networks and tradeoff multiple design considerations such as metal resource allocation on chip and in package, decoupling capacitor insertion and I/O allocation. Such studies can be performed during early stages of design, even when detailed physical design information is not available. The models are used to model a ceramic package designed by IBM, and it is found that there is less than 10% difference between the model predictions and the commercial tool SPEED 2000 when predicting the peak noise value and time of occurrence. The models can have 10times speed-up compared to SPEED 2000.

High performance thin film single chip module

This paper describes development of high density single chip modules for flip chip (C4) area array interconnect such that the electrical, thermal, and reliability needs are met through an optimal tradeoff between system performance and module cost. Prototype test vehicles were designed and built using co-fired alumina as the base carrier for two levels of copper-polyimide thin films containing the bulk of signal wiring and a power/ground plane. Flip-chip die with high melt bumps were joined directly to copper pads on the thin film substrate. Reliability aspects of this interconnect product, such as, wettability and joinability characteristics of thin Cu films and integrity of thin film via interconnections as a function of pre- and post-thermal cycling have been studied. Also, module encapsulation aspects are briefly discussed. The results of electrical characterization of the thin film substrate prior to die attach, as well as simultaneous switching noise measurements with a functional test die are presented.