Ajay P. Giri

Thin-film multichip module packages for high-end IBM servers

A new generation of multilevel thin-film packages has been developed for IBM high-end S/390® and AS/400® systems. Thin-film structures in these packages are nonplanar and can be fabricated by either pattern electroplating or subtractive etching. Selection criteria for choice of fabrication methods are discussed in terms of electrical performance requirements, ground rules, manufacturability, and cost issues. Two problems encountered in the development phase of the nonplanar thin-film structures were 1) accelerated etching of plated Cu features during Cu seed etching, and 2) corrosion of the bottom-surface metallurgy during etching of Cr at the top surface. Effective solutions were developed on the basis of underlying electrochemical phenomena. Finally, reliability stress procedures used to qualify these packages and results of these procedures are presented.

Development and Implementation of C4NP Technology for 300 mm Wafers

Considerable work is ongoing worldwide on developing lead-free solutions for electronics industry to meet the needs of RoHs requirements. This paper describes the development and implementation of lead-free C4 interconnects for 300 mm wafers using, C4NP technology at IBM with equipment partnership with Suss MicroTech Inc. Key process modules of C4NP technology are: (a) UBM pads fabrication using simple unit processes in back end of the line semiconductor manufacturing facility, (b) Solder melt filling of glass molds with cavities in solder fill tool and inspection, (c) C4 bump transfer to UBM pads on wafers using vaporized flux process in solder transfer tool, (d) Final inspections and electrical tests. This process technology for C4 bumping eliminates the need for solder or solder alloy plating and provides wider latitude for selecting solder composition. For example, solders can be selected for improved mechanical properties and, or low alpha emission requirements. This can be accomplished by simple changing of mold fill head. Primary efforts of this study are focused on four key elements: (1) Development of unit processes for UBM pad patterning and solder transfer processing, (2) chip/organic laminate module builds, using industry standard bond and assembly processes, (3) selection of specific test vehicle wafers with 200 um pitch pads and over 1.25 million C4 bumps, and (4) extensive reliability testing of modules with JDEC and IBM internal standards. Modules with test vehicle chips as well as product chips have shown excellent reliability data, comparable to that of high lead electroplated C4 bumps, and meet application requirements. In order to assess manufacturing robustness and yields, sector partitioning studies were undertaken to understand the effects of unit process windows and defect densities. Results show that C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Technology qualification studies have been successfully completed. Thus, enabling the path for manufacturing ramp up. This technology is extendable to higher density C4 interconnects and product qualifications studies on C4 bumps on 150 um pitch are ongoing. IBM is adapting this technology for 300 mm lead-free applications.

High performance thin film single chip module

This paper describes development of high density single chip modules for flip chip (C4) area array interconnect such that the electrical, thermal, and reliability needs are met through an optimal tradeoff between system performance and module cost. Prototype test vehicles were designed and built using co-fired alumina as the base carrier for two levels of copper-polyimide thin films containing the bulk of signal wiring and a power/ground plane. Flip-chip die with high melt bumps were joined directly to copper pads on the thin film substrate. Reliability aspects of this interconnect product, such as, wettability and joinability characteristics of thin Cu films and integrity of thin film via interconnections as a function of pre- and post-thermal cycling have been studied. Also, module encapsulation aspects are briefly discussed. The results of electrical characterization of the thin film substrate prior to die attach, as well as simultaneous switching noise measurements with a functional test die are presented.