Daniel Vanderstraeten

Sub-pixel image correlation: an alternative to SAM and dye penetrant for crack detection and mechanical stress localisation in semiconductor packages

Sub-pixel image correlation has been applied to the measurement of surface deformation, in particular to the measurement of thermally induced strain in microchips. A Fourier shift technique coupled with successive approximation is used to determine the sub-pixel component of the deformation. This reduces the effects of systematic errors on data associated with interpolation or curve-fitting present in other sub-pixel techniques. For all image correlation techniques, defocus errors can have serious effects on the accuracy of the technique. These errors are eliminated in this case through use of a set of images at different axial positions, where only the in focus information is used. This allows determination of the out-of-plane component of the displacement to within roughly 1/40 of the depth of focus (250 nm at ×10 magnification). An in-plane deformation/displacement uncertainty of roughly 2% of a pixel (<15 nm at ×10 magnification) is achievable on real-world samples.

On the impact of the edge profile of interconnects on the occurrence of passivation cracks of plastic-encapsulated electronic power devices

Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic-packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time the impact of the edge profile of the power metal design on the amount of passivation cracks was investigated in detail. It was found that with a sloped edge profile of the power metal, as it is achieved with a combination of an isotropic wet etch followed by a dry etch, the number of passivation cracks is reduced significantly. The observation is confirmed by a 3-D FEM simulation. The simulation enabled to quantify the stress level and to forecast corresponding levels of cracks observed after temperature cycling. As a result, a robust metal edge profile design could be deduced, which led to a distinct reduction of the principal stress at the most critical positions and, consequently, to a reduction of passivation damage.

Comparison of experimental methods for the extraction of the elastic modulus of molding compounds used in IC packaging

Knowing the Young’s modulus of a plastic molding compound and how it evolves over time and with temperature provides valuable information since it has an important impact on the thermo-mechanical stress that is imposed on a packaged IC. This paper demonstrates the utilization of two techniques that can offer fast, easy and straightforward methods for Young’s modulus extraction of plastic molding compound materials. Both techniques are additionally compared with the nano-indentation (NI) method. Each of these techniques have their advantages and limitations, and therefore, the criterion to select the most appropriate technique for Young’s modulus extraction depends on several parameters like sample preparation time, measurement time and the number of measurements needed to have good statistics. The originality of this study lies in the fact that the evaluation of these methods focuses not only on Young’s modulus extraction from bare molding compound material, but also from molding compounds on packaged IC’s as well.

Development of fast and easy methods for measuring the Young's modulus of molding compounds for IC packages

This work presents two different methods that offer a faster, easier and more straightforward data analysis methods for Youngs modulus extraction of plastic molding compound materials. Both methods are compared and verified with the nano-indentation (NI) technique. The originality of this study lies in the fact that the evaluation of these methods focuses not only on Youngs modulus extraction from bare molding compound material, but also of molding compounds of packaged ICs as well. The results show also that the NI data analysis is not straightforward due to the inhomogeneous mixture of the different types of materials and fillers inside the molding compound, hence resulting in a complex and rather unknown deformation behavior upon indentation.

Impact of the leadframe profile on the occurrence of passivation cracks of plastic-encapsulated electronic power devices

Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time the impact of the leadframe profile on the amount of electrical failures after thermal cycling (TC) was investigated in detail. It was found that with a trench in the leadframe on the perimeter of the Si die with the power switching device, the number of electrical failures have been eliminated completely. The observation is confirmed by 3-D Finite Element Modeling (FEM) simulation. The simulation enabled to quantify the stress level and to forecast corresponding electrical failures observed after temperature cycling. As a result, an improved leadframe design could be deduced, which led to a distinct reduction of the principal stress at the most critical positions and, consequently, to an improvement of the reliability of the devices.

Impact of thermal ageing on cohesive and adhesive strengths of overmould materials: Characterisation methods and implementation in FEM

This paper reports the impact of ageing on the cohesive and adhesive strength of overmould materials used in electronic packages. For so-called harsh environment applications, the overmoulded package operates in an ambient at a continuous temperature of 175°C, or sometimes even 200°C. At these high temperatures, it can be expected that the overmould material and its interfaces degrade. In order to select the right overmould materials, ageing tests have been performed on different commercially available materials. Static bending experiments are used to measure the elastic modulus, the ultimate strength and the interface strength. The impact of the materials properties changed by thermal ageing, are implemented in Finite Element Models. For a particular package, the study shows after how many hours of ageing, the stresses can lead to overmould cracking.

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Temperature distribution in diced and packaged DMOS devices subjected to repetitive stress is analyzed using transient interferometric mapping (TIM) technique combined with measurements on diode built-in temperature sensors. The effect of DMOS device position on dice, duty cycle and chip ambient temperature on thermal distribution is studied. The TIM experiments and transient temperature measurements are in good agreement with numerical 3D thermal simulations. Failure analysis data after long term pulse stress testing indicate electromigration degradation of the top metal.

Flip chip based packaging solution for high current driver chips used in automotive applications

In this work, flip chip is investigated as an alternative assembly technology for packaging applications requiring driving high electrical currents up to 10A and high IC power dissipation. Currently, automotive applications with components driving (temporary) high electric currents are mainly using wire bond based packaging solutions because of cost reason. However, wire bonds with standard diameters are limited in their capability of driving large currents due to the joule heating, which results in unacceptable high temperatures as shown in this paper by analytical calculations, non linear finite element model simulations and experiments on test packages. The temperature increase exponentially grows with current due to the joule heating effect. The flip chip assembly with lead-free solder interconnects, thick top metallization on the die and adapted PCB has proven to be capable to drive currents up to 10A without substantial temperature increase.