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Dive into the research topics where Renaud Gillon is active.

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Featured researches published by Renaud Gillon.


IEEE Transactions on Electron Devices | 1998

Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling

Jean-Pierre Raskin; Renaud Gillon; J. Chen; Danielle Vanhoenacker-Janvier; Jean-Pierre Colinge

The maturation of low-cost silicon-on-insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs. The extracted model is shown to be valid up to 40 GHz.


IEEE Microwave and Guided Wave Letters | 1997

Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFETs

Jean-Pierre Raskin; G. Dambrine; Renaud Gillon

A new extraction scheme is proposed which allows to determine all the series equivalent circuit elements values from S-parameters measurements at a single bias point in saturation. Exploiting the specific shape of a set of impedance loci, the new scheme uses linear regression techniques to solve the extraction problem. The resulting algorithm is very simple and efficient when compared to optimizer-driven approaches.


IEEE Transactions on Electron Devices | 2007

Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs

Yogesh Singh Chauhan; F. Krummenacher; Renaud Gillon; Benoit Bakeroot; M. Declercq; Adrian M. Ionescu

This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on CGD, CGS, and CGG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).


international conference on simulation of semiconductor processes and devices | 2002

Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET

N. Hefyene; E Vestiel; Benoit Bakeroot; C. Anghel; S. Frere; Adrian M. Ionescu; Renaud Gillon

A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.


european solid-state device research conference | 2001

Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage

C. Anghel; N. Hefyene; Adrian M. Ionescu; Miguel Vermandel; Benoit Bakeroot; Jan Doutreloigne; Renaud Gillon; S. Frere; Christian Maier; Y Mourier

Thorough investigations of the saturation phenomena in state-of-the-art HV Lateral DMOS architectures (L-DMOS and X-DMOS), based on 2D numerical simulation and on the new concept of intrinsic drain potential, VK, are presented The paper highlights the VK evolution in all operation regimes, analyses the corresponding complex quasi-saturation mechanisms and originally demonstrates that this key potential remains at a low-voltage and shows a marked maximum value at low Vc. A simple and accurate analytical modelling strategy, which is usable for any architecturexad specific bias-dependence of the drift region equivalent resistance is proposed based on the VK-concept. Very good model performances using a BSIM3v3 low-voltage model combined with the proposed intrinsic MOSFET strategy are reported


IEEE Electron Device Letters | 2006

New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

C. Anghel; Benoit Bakeroot; Yogesh Singh Chauhan; Renaud Gillon; Christian Maier; Peter Moens; Jan Doutreloigne; Adrian Mihaim Ionescu

This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.


international semiconductor conference | 2001

Physical modelling strategy for (quasi-) saturation effects in lateral DMOS transistor based on the concept of intrinsic drain voltage

C. Anghel; N. Hefyene; Am Ionescu; Miguel Vermandel; Benoit Bakeroot; Jan Doutreloigne; Renaud Gillon; S. Frere; Christian Maier; Y Mourier

This paper deals with the investigation of the LDMOSFET saturation mechanisms via 2D numerical simulations and experiments. A clear separation between the saturation of intrinsic MOS transistor and complex quasi-saturation mechanisms is made using the intrinsic drain concept. A modelling strategy for drain current based on the experimental extraction of the drift series resistance is presented. Very good model performances using a BSIM3v3 low voltage model combined with the proposed drift resistance extracted values are reported.


european solid state device research conference | 2007

Impact of lateral non-uniform doping and hot carrier degradation on capacitance behavior of high voltage MOSFETs

Yogesh Singh Chauhan; Renaud Gillon; M. Declercq; Adrian M. Ionescu

In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in CGD and CGS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the CGD capacitance and increases the peaks in CGS and also gives rise to peaks in CGG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.


Iete Technical Review | 2008

Impact of Lateral Nonuniform Doping and Hot Carrier Injection on Capacitance Behavior of High Voltage MOSFETs

Yogesh Singh Chauhan; Renaud Gillon; M. Declercq; Adrian M. Ionescu

Abstract A detailed analysis of capacitance behavior of high-voltage MOSFET (HV-MOS), for example, LDMOS, using device simulation is made. The impact of lateral nonuniform doping and drift region are separately analyzed. It is shown that the peaks in CGD and CGS capacitances of HV-MOS originate from lateral nonuniform doping. The peak value of CDG capacitance can be higher than WLCox for nonzero drain biases. The drift region decreases the CGD capacitance and increases the peaks in CGS in strong inversion and also gives rise to peaks in CGG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier injection modulates the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.


international semiconductor conference | 2003

Electrical characterisation of high voltage MOSFETs using MESDRIFT

C. Anghel; N. Hefyene; Miguel Vermandel; Benoit Bakeroot; Jan Doutreloigne; Renaud Gillon; Am Ionescu

This paper deals with the degradation mechanisms of 100V Lateral DMOSFETs proposing a new test structure called MESDRIFT, test structure concept designed and fabricated by AMIS, Belgium. This structure presents a small contact smartly engineered at the separation boundary between the intrinsic MOS and drift zone. The contact allows the separate investigation of the parts without altering the overall characteristics of the original device. Experiments; performed on MESDRIFT revealed that hot holes/electrons are injected into the oxide for low/high V/sub G/, high V/sub D/ stress conditions. 2D numerical simulations were used to reinforce the theory behind the degradation mechanisms of these devices.

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Benoit Bakeroot

Katholieke Universiteit Leuven

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Adrian M. Ionescu

École Polytechnique Fédérale de Lausanne

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C. Anghel

École Polytechnique Fédérale de Lausanne

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Yogesh Singh Chauhan

Indian Institute of Technology Kanpur

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Jean-Pierre Raskin

Université catholique de Louvain

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M. Declercq

École Polytechnique Fédérale de Lausanne

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