Daniel W. Bechtle

Investigation of active antenna arrays at 60 GHz

There has been a significant effort to develop millimeter-wave active-array antennas for communications and radar applications. A dielectric waveguide is a promising medium for this application. However, the integration of active devices, transmission media, and antennas has been difficult to achieve. This paper presents the first successful demonstration of a phase locked array of millimeter wave grating surface emitters (MMWGSE). We discuss three aspects of MMWGSE: (1) The achievement of an optically steered millimeter wave grating surface emitter. (2) The demonstration of a frequency locked array of millimeter wave grating surface emitters. (3) Rigorous analytical studies of efficiently coupling power from a millimeter wave semiconductor device, to a waveguide which incorporates grating surface emitters. This work leads to a full monolithic array using pseudomorphic high electron mobility transistor (PHEMT)-devices. >

2-4 GHz monolithic lateral p-i-n photodetector and MESFET amplifier on GaAs-on-Si

The design, fabrication, and evaluation of broadband lateral p-i-n photodetectors monolithically integrated with multistage MESFET amplifiers on GaAs-on-Si are described. Unique features of this approach are that (a) the lateral p-i-n structure is compatible with monolithic microwave integrated circuit (MMIC) technology and (b) the p-i-n detector is fabricated directly on the GaAs buffer layer without p/sup +/ and n/sup +/ implants, thus resulting in a simplified fabrication process. The operation of the circuit is compared to that of a similar circuit fabricated on a GaAs substrate. A quantum efficiency exceeding 60% has been measured for the p-i-n detectors. The 2- to 4-GHz frequency responses of one- and two-stage p-i-n/FET preamplifiers are presented. The response varies +or-3 dB over the frequency band. >

High-efficiency 35-GHz GaAs MESFET's

Ka-band GaAs FETs with power output in excess of 200 mW and with efficiencies of more than 20 percent are described. Both ion-implanted and VPE-grown wafers were used. Deep UV (300-nm) lithography and chemical etching was employed to obtain a final gate length of 0.5 µm. These FET chips were flip-chip mounted and had a very low thermal resistance of 50°C/W for a total source periphery of 0.6 mm. At 35 GHz an output power of 220 mW with 21-percent efficiency at 3-dB gain was obtained from a 0.6-mm cell.

Novel selective-plated heatsink, key to compact 2-watt MMIC amplifier

We describe an improved heatsink technology fully compatible with a standard MMIC processing that significantly decreases the thermal limitation of the MMIC format. By etching to reduce the substrate thickness by 75 micron only immediately under the active areas of the MESFETs and selectively plating solid gold heatsinks to replanarize the back of the wafer, a 45 percent reduction in the thermal resistance is obtained. Despite a very compact design, 2.4 mm MESFETs fabricated on 100 micron thick substrates demonstrated a thermal resistance of only 18 C/W. Using these devices, a 2 stage 2 watt power MMIC was designed to fit a compact 1.4 mm x 3.25 mm chip footprint. The nominal 2 watt, 7-11 GHz power MMIC amplifier was designed for phased array applications where small size, high power and high efficiency are primary concerns. With fixed off-chip tuning, the MMIC delivers 1.7-2.3 watts with 18-24 percent power added efficiency across the full 7-11 GHz band.

Wide-band GaInAs MISFET amplifiers

The authors present the first reported results on wideband GaInAs MISFET amplifiers. Using 1- mu m-gate-length, 0.56-mm-gate-width GaInAs MISFETs, they obtained: (a) a power output of 230+or-30 mW (0.41 W/mm) with 33+or-3% power-added efficiency; (b) a power output of 265+or-15 mW (0.47 W/mm) with 30+or-3% power-added efficiency (both over the 7-11-GHz band), and (c) a power output of 220+or-45 mW (0.39 W/mm) with 32+or-4% power-added efficiency over the 6-12-GHz band. With a 0.7- mu m-gate-length GaInAs MISFET, a small-signal gain of 5+or-0.5 dB over the 11.4-22.6-GHz band was obtained. These data include all connector, bias network, and circuit losses. The authors present an equivalent circuit model of these MISFETs based on S-parameter measurements. The model is essentially that of a MISFET with capacitors representing gate-to-source and gate-to-drain overlap capacitances added at input and output. >

Compact high-power low-jitter semiconductor mode-locked laser module for photonic A/D converter applications

Low-capacitance, two-section, curved-waveguide gain elements were packaged with lensed polarization-maintaining fiber within standard-sized butterfly-style packages and shown to produce low-jitter pulses when used within a harmonically modelocked sigma cavity laser (jitter = 25 fs; 10 Hz - 10 MHz). Incorporation of a high finesse etalon filter into the sigma-cavity loop resulted in greater than 25 dB suppression of the supermode spurs while maintaining low integrated phase noise (jitter = 30 fs; 10 Hz - 10 MHz). A module containing the in-line sigma-cavity modelocked laser source and packaged semiconductor optical amplifiers was developed to create a configurable low jitter pulse source.

GaInAs MISFET Wideband Microwave Power Amplifiers

We present the first reported results on wideband GaInAs MISFET amplifiers. Using 1-μm-gatelength, 0.56-mm-gatewidth GaInAs MISFETs, we obtained: (a) a power output of 230±30mW (0.41 W/mm) with 33±3% power-added efficiency; (b) power output of 265±15 mW (0.47 W/mm) with 30±3% power-added efficiency, both over the 7- to 11- GHz band, and (c) a power output of 220 ±45 mW (0.39 W/mm) with 29 ±4% power-added efficiency over the 6- to 12-GHz band. With a 0.7-μm-gatelength GaInAs MISFET, a small-signal gain of 5±0.5 dB over the 11.4- to 22.6-GHz band was obtained. These data include all connector, bias network, and circuit losses. We also present an equivalent circuit model of 1-μm-gatelength GaInAs MISFETs based on S-parameter measurements. The model is essentially that for a MESFET with capacitors representing gate-to-source and gate-to-drain overlap capacitances added at input and output.