Danilo Manstretta

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

Low 1/f noise CMOS active mixers for direct conversion

The analysis of direct conversion CMOS active mixers tailored to ReFlex standard is presented. To minimize 1/f noise, the switching stage pMOS devices have large area, low biasing current. pMOS and nMOS transconductors shunted together form the input stage. A 0.35-/spl mu/m prototype performs at 900 MHz as follows: 18 dB SSB NF averaged in the 100 Hz-3 kHz band, 18 dB gain, -4-dBm IIP3, 30-dBm IIP2 with 6 mA from 2.7-V supply.

A 0.18/spl mu/m CMOS direct-conversion receiver front-end for UMTS

The authors present a direct-conversion receiver front-end IC which contains LNA, quadrature mixers and VGAs, realized in 0.18 μm CMOS technology. It has +48.8 dBm IIP2, -6 dBm in band IIP3 (-2 dBm out of band 113), 6.2 dB DSB NF integrated in a 10 kHz-1.92 MHz band and draws 15 mA from a 1.8 V supply.

A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.

An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators

An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the actual one is derived for all topologies considered. Measurements on a dedicated chip prototype that integrates two high performance topologies allow to verify, in an unbiased way, the accuracy of the predictions. A very good agreement between the model and both simulation and measurement is obtained.

A low-noise active balun with IM2 cancellation for multiband portable DVB-H receivers

Broadband low noise amplifiers are needed in a variety of applications, from multistandard cellular receivers to terrestrial and handheld TV tuners [1,2]. For broadband and multiband operation, intermodulation and cross-modulation impose additional linearity requirements to the RF front-end [2,3]. In a multiband DVB-H receiver covering both VHF-III (from 170 to 230MHz) and UHF IV–V (from 470 to 890MHz) receive bands [4], cross-modulation between VHF III and UHF IV–V channels gives rise to second order intermodulation distortion (IM2) products that fall from 650MHz up to 890MHz, covering most of the UHF IV–V band. Cross-modulation between UHF IV–V band channels gives rise to IM2 products covering the whole VHF-III band. The most stringent second-order intermodulation intercept point (IIP2) requirement is given by single-tone S2 test patterns [4]: the maximum interferer level for a portable receiver (class b2, c) is −28dBm, 42dB above the desired signal. Assuming a 5dB NF and a minimum SNR of 12.7dB, the minimum IIP2 is 26.8dBm. The most stringent IIP3 requirement is set by L2, L4 test patterns: the maximum interferer level is −35dBm, 47dB above the desired channel, resulting in a minimum IIP3 of −4.4dBm.

Analysis and optimization of IIP2 in CMOS direct down-converters

Two mechanisms are responsible for second order intermodulation in CMOS down-converters: RF self-mixing and device non-linearity and mismatches. An intuitive model and analytical expressions are provided for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8 V supply, part of a fully integrated 0.18 /spl mu/m CMOS UMTS receiver front-end shows 66 dBm IIP2 and 16 dBm IIP3.

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

A complementary p-n class-B oscillator with two magnetically coupled second harmonic tail resonators is presented and compared to an N-only reference one. An in depth analysis of phase noise, based on direct derivation of the Impulse Sensitivity Function (ISF), provides design insights on the optimization of the tail resonators. In principle the complementary p-n oscillator has the same optimum Figure of Merit (FoM) of the N-only at half the voltage swing. At a supply voltage of 1.5 V, the maximum allowed oscillation amplitude of the N-only is constrained, by reliability considerations, to be smaller than the value that corresponds to the optimum FoM even when 1.8 V thick oxide transistors are used. For an oscillation amplitude that ensures reliable operation and the same tank, the p-n oscillator achieves a FoM 2 to 3 dB better than the N, only depending on the safety margin taken in the design. After frequency division by 2, the p-n oscillator has a measured phase noise that ranges from -150.8 to -151.5 dBc/Hz at 10 MHz offset from the carrier when the frequency of oscillation is varied from 7.35 to 8.4 GHz. With a power consumption of 6.3 mW, a peak FoM of 195.6 dBc/Hz is achieved.

Analysis and Design of a 54 GHz Distributed “Hybrid” Wave Oscillator Array With Quadrature Outputs

An array of distributed oscillators for millimeter-wave phased arrays combines local oscillator (LO) generation and distribution, leading to a phase noise improvement proportional to the number of array elements. The unit “hybrid wave” oscillator (HWO) consists of a rotary traveling-wave oscillator with quadrature outputs, coupled to the other units through standing-wave oscillators. A phase noise analysis for distributed oscillators based on impulse-sensitivity functions (ISF) is introduced and applied to study the proposed oscillator and arrays of it. A standalone oscillator and a 4-elements array implemented in a 65 nm CMOS technology have a measured phase noise of -125 dBc/Hz and -131 dBc/Hz respectively at 10 MHz from the 52 GHz carrier. Each unit consumes 36 mW corresponding to a FoM of -183.7 dBc/Hz. The tuning range is from 51.9 to 56.5 GHz.