Francesco Svelto

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.

Analysis and design of injection-locked LC dividers for quadrature generation

Injection-locked LC dividers for low-power quadrature generation are discussed in this paper. Modeling the circuits as regenerative frequency dividers leads to very simple analytical expressions for the locking band, phase deviation from quadrature and phase noise. Maximizing the ratio between the injected and the biasing current is beneficial to all the above parameters whereas reducing the tank quality factor improves locking band and quadrature accuracy, though at the expense of current consumption, for given output amplitude. To validate the theory, experiments have been carried on a 0.18-/spl mu/m CMOS direct conversion IC, embedding an injection-locked quadrature generator, realized for the Universal Mobile Telecommunication System. Frequency locking range as large as 24% and phase deviation from quadrature around 0.8/spl deg/ are measured while each divider consumes 2 mA. The phase noise of the quadrature generator is determined by the driving oscillator phase noise because the dividers contribution is easily made negligible up to hundreds of megahertz offset.

Analysis of reliability and power efficiency in cascode class-E PAs

Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-/spl mu/m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Bluetooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Bluetooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Bluetooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 /spl mu/m CMOS technology are presented and discussed.

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm2 in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO

This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the component spread, due to process variations, can be done. The LC tank is made of a metal-oxide-silicon varactor and a bondwire and a spiral inductor in series. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2-V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1-1.45 G-Hz. The measured phase noise at an offset of 600 kHz from a 1.3-GHz carrier is -119 dBc/Hz, with 6-mA current consumption.

A metal-oxide-semiconductor varactor

CMOS technology scaling opens up the possibility of designing variable capacitors based on a metal oxide semiconductor structure with improved tuning range and quality factor. This is due to an increase in the oxide capacitance and a reduction in the parasitic resistance. A prototype metal-oxide-semiconductor (MOS) variable capacitor of 3.1 pF nominal value has been realized in a 0.35-/spl mu/m standard CMOS process. A factor two capacitance change has been achieved for a 2-V variation of the controlling voltage. The varactor Q ranges from 17 to 35, at 1.8 GHz.

A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications

Employing feedback circuits in RF front-ends can be a key aspect for easy reconfiguration of multistandard receivers. A narrow-band filter can shape the frequency transfer function and, by reflection due to the feedback network, the input impedance. Switching one single filter component thus allows selecting a different standard. We introduce a voltage-voltage feedback low noise amplifier that, besides being easily reconfigurable, shows roughly the same noise and better linearity, for same power consumption, as the conventional inductively degenerated topology. A direct conversion front-end, including the LNA and I and Q mixers, tailored to WLAN applications in the 5-6 GHz range, has been realized in a 0.25-/spl mu/m SiGe BiCMOS process. Prototypes show the following performances: 2.5 dB NF, 31.5 dB gain, -9.5dBm IIP3, and +23dBm minimum IIP2 while consuming 16 mA from a 2.5 V supply.

A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers

The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs. Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-/spl mu/m CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower. Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV//spl radic/Hz input referred noise voltage density while drawing 4 mA from 1.8 V.

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the authors knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.