Danko Ivosevic

Unified flow of custom processor design and FPGA implementation

The automation of custom hardware design often focuses on hardware optimizations for smaller portions of code that dominate the design execution. The same presumption can be stated for custom processor design. The data path of the processor can be well optimized for particular blocks of code that are formed during control flow extraction. However, larger source codes can have tens of blocks that result from Control Flow Graph (CFG). We implemented a global semi-automated flow that hierarchically forms the set of blocks which contributions are modeled into processor architecture. Resulting processor model is translated to RTL description and implemented inside FPGA logic.

Performance estimation in heterogeneous MPSoC based on elementary operation cost

Effective use of resources available on heterogeneous MPSoC platforms can only be achieved through careful resource allocation and scheduling. The diversity of processing and memory elements will manifest itself in the total time and resources required to perform a task or execute an application. Choosing the right platform element is the key and the first step is performance estimation. This paper tackles the issue of finding the most suitable processing element for each part of the software application through a novel approach - elementary operation cost. The cost of each elementary operation is experimentally determined through a set of carefully devised benchmarks and is used for estimating duration of complex functions found in common applications such as JPEG, AES etc. By raising the abstraction level on which the execution time is calculated from instruction to operation level, common problems in performance estimation such as pipelining and branch prediction can be avoided and estimation accuracy is improved. Demonstrated results show that the average error rate of estimated execution times for various benchmarks is around six percent compared to the actual execution times.

Function-level performance estimation for heterogeneous MPSoC platforms

Main challenge of system-level design is fast and accurate performance estimation on heterogeneous multiprocessor system-on-chip (MPSoC) platforms in early design stages. In this paper the authors present a design flow of a novel framework for automated early high-level software performance estimation based on source code analysis using elementary operation concept. The tools implemented within the framework support performance evaluation by application C code intermediate representation analysis and production of profiling data per single line of code instruction. The concept of elementary operation usage in gaining the appropriate application profiling is tested on two processor cores as representatives of different processing elements often used inside MPSoC platforms. Preliminary results demonstrate the ability to provide fast and efficient design space exploration with high accuracy of performance estimation.

Heterogeneity impact on MPSoC platforms performance

Embedded systems have become an integral part of High Performance Computing (HPC) due to their appealing energy and resource consumption characteristics. Required performance goals can be achieved only by deploying the application on a heterogeneous platform. The established approach of designing a custom made FPGA architecture platform targeting particular application is challenged by novel multiprocessor heterogeneous platforms built using existing of-the-shelf embedded CPUs. The challenge is to exploit all the available parallelism and heterogeneity to design a time and cost efficient, but also a reusable solution which will meet the performance goals. In this paper the heterogeneity of parallel SoC system is evaluated through different processor cores and memory configurations usage examination. The design space exploration undertaken relies on several hypotheses concerning design concepts relations. Since system operating frequency is crucial, but not the only design performance success parameter, the importance of operating processor data path is emphasized as it conducts the application mapping approach. We show that, depending on the different heterogeneous elements configurations used within some multicore SoC solution, the suitability of particular processor cores usage varies on application type, but with achieved performance comparable to application-specific custom generated hardware.

Time domain performance evaluation of adaptive hybrid cache coherence protocols

Adaptive hybrid cache coherence protocols use both the write-invalidate mechanism and the write-update mechanism to maintain coherence among copies of data objects. Each of these protocols implements a decision function that chooses the appropriate mechanism in order to improve their performance. In most existing solutions, decision functions are based on communication traffic. Moreover, the authors of the adaptive protocols use communication traffic as a performance measure in their papers. In contrast, in this paper we present the results of a performance evaluation of adaptive hybrid cache coherence protocols in both the traffic domain and in the time domain. We compare three adaptive protocols with pure write invalidate and pure write-update protocols. Let r/sub WI/, r/sub WU/, and r/sub A/ be the average communication traffic per access for the write-invalidate protocol, the write-update protocol, and the adaptive protocol, respectively. The adaptive protocol minimizes the traffic if r/sub A//spl ap/min(r/sub WI/, r/sub WU/). Similarly, the adaptive protocol minimizes the access latency if t/sub A//spl ap/min(t/sub WI/, t/sub WU/), where t/sub WI/, t/sub WU/, and t/sub A/ are the access latencies for the write-invalidate protocol, the write-update protocol, and adaptive protocol, respectively. For some of the workload parameters the adaptive protocols minimize both traffic and access latency. However, we also present and analyze the workload parameters for which adaptive protocols minimize communication traffic, but fail to minimize the access latency.

Performance-Occupation trade-off examination in custom processor design

Trade-off between execution time and resource occupation arise in all kinds of digital system designs. Here we present such relation for FPGA-based custom processor design. Usually, the optimal tradeoff is directed by device sizing on all scales of the design, but for FPGA device, as predefined hardware platform, it is more focused on comparison of existing platforms organizations. The customization of processor architecture as a point of design performance improvement is usually focused on selection of parameter set that governs the most the design characteristics. In this paper, the focus is on processor architecture datapath with predefined design template and relationship of its structure to final FPGA implementation it maps to. For purpose of evaluation of multiple design at the same time, the appropriate software flow is applied to construct the design space based on constraining of datapath functional units operation types. The data are collected throughout the whole design flow starting from input control and data flow characteristics of the application and ending with FPGA implementation data. The analysis of the design flow showed dependence of final implementation on datapath structure and its components complexities.