Nikolina Frid

Unified, multiple target, computer engineering learning platform

To overcome a complex and multidisciplinary approach which includes understanding of various systems based on different technologies and system solution optimizations in engineering education for embedded systems at university level and provide a complex and multidisciplinary approach, the first cycle of the design of a unified, multiple-target platform that will enable integrated approach to computer engineering and embedded systems learning has been finished so far. This work shows results of current research, preliminary conclusions and future focuses.

Critical path method based heuristics for mapping application software onto heterogeneous MPSoCs

In this paper the authors propose new heuristics for automation of software partitioning and mapping onto heterogeneous multiprocessor System-on-Chip (MPSoC) platform - Longest Parallel Path mapping algorithm (LPP). In contrast with traditional approach to solving this NP-complete problem - the Integer Linear Programming (ILP), our method uses a modified version of Critical Path Method with additional heuristics that rely on greedy approach. The algorithm performs one-to-many mapping of application to platform with minimizing the overall execution time of the application as the main objective. Our experiments with generic application model and several different platform layouts show that the proposed algorithm provides an efficient mapping scheme enabling significant execution speedup. In addition, the comparison with another greedy mapping algorithm shows that LPP algorithm exploits available task level parallelism better.

Performance estimation in heterogeneous MPSoC based on elementary operation cost

Effective use of resources available on heterogeneous MPSoC platforms can only be achieved through careful resource allocation and scheduling. The diversity of processing and memory elements will manifest itself in the total time and resources required to perform a task or execute an application. Choosing the right platform element is the key and the first step is performance estimation. This paper tackles the issue of finding the most suitable processing element for each part of the software application through a novel approach - elementary operation cost. The cost of each elementary operation is experimentally determined through a set of carefully devised benchmarks and is used for estimating duration of complex functions found in common applications such as JPEG, AES etc. By raising the abstraction level on which the execution time is calculated from instruction to operation level, common problems in performance estimation such as pipelining and branch prediction can be avoided and estimation accuracy is improved. Demonstrated results show that the average error rate of estimated execution times for various benchmarks is around six percent compared to the actual execution times.

Function-level performance estimation for heterogeneous MPSoC platforms

Main challenge of system-level design is fast and accurate performance estimation on heterogeneous multiprocessor system-on-chip (MPSoC) platforms in early design stages. In this paper the authors present a design flow of a novel framework for automated early high-level software performance estimation based on source code analysis using elementary operation concept. The tools implemented within the framework support performance evaluation by application C code intermediate representation analysis and production of profiling data per single line of code instruction. The concept of elementary operation usage in gaining the appropriate application profiling is tested on two processor cores as representatives of different processing elements often used inside MPSoC platforms. Preliminary results demonstrate the ability to provide fast and efficient design space exploration with high accuracy of performance estimation.

Heterogeneity impact on MPSoC platforms performance

Embedded systems have become an integral part of High Performance Computing (HPC) due to their appealing energy and resource consumption characteristics. Required performance goals can be achieved only by deploying the application on a heterogeneous platform. The established approach of designing a custom made FPGA architecture platform targeting particular application is challenged by novel multiprocessor heterogeneous platforms built using existing of-the-shelf embedded CPUs. The challenge is to exploit all the available parallelism and heterogeneity to design a time and cost efficient, but also a reusable solution which will meet the performance goals. In this paper the heterogeneity of parallel SoC system is evaluated through different processor cores and memory configurations usage examination. The design space exploration undertaken relies on several hypotheses concerning design concepts relations. Since system operating frequency is crucial, but not the only design performance success parameter, the importance of operating processor data path is emphasized as it conducts the application mapping approach. We show that, depending on the different heterogeneous elements configurations used within some multicore SoC solution, the suitability of particular processor cores usage varies on application type, but with achieved performance comparable to application-specific custom generated hardware.

Computer Engineering Laboratory Course: E2LP Platform Experience.

In this paper, the preliminary results of E2LP Base Board platform introduction to students of Faculty of EE and Computing master programme enrolled in Laboratory of Computer Engineering 2 course are presented and discussed. The aim of introduction of new hardware unified platform was to improve practical skills and experience in embedded system design. The students embraced the new platform with enthusiasm and were eager to give the feedback in order to point out the strengths and weaknesses of this platform. The collected information will be a valuable asset for future improvement of the platform.

Work in progress: Embedded computer engineering learning platform capabilities

Provided unified learning platform, which is developed as a main goal of our ICT FP7 - Collaborative Project: Embedded Computer Engineering Learning Platform enables modular approach in education of computer engineers. It helps engineering education personnel to transform passive listeners students into active learners, thus stimulating students to actively participate in the learning process. Furthermore, this platform shall introduce a flexible and extendable learning environment for upcoming technologies in embedded systems, thus providing a long lasting educational solution for academia. This work in progress article describes capabilities of our learning platform.

Performance-Occupation trade-off examination in custom processor design

Trade-off between execution time and resource occupation arise in all kinds of digital system designs. Here we present such relation for FPGA-based custom processor design. Usually, the optimal tradeoff is directed by device sizing on all scales of the design, but for FPGA device, as predefined hardware platform, it is more focused on comparison of existing platforms organizations. The customization of processor architecture as a point of design performance improvement is usually focused on selection of parameter set that governs the most the design characteristics. In this paper, the focus is on processor architecture datapath with predefined design template and relationship of its structure to final FPGA implementation it maps to. For purpose of evaluation of multiple design at the same time, the appropriate software flow is applied to construct the design space based on constraining of datapath functional units operation types. The data are collected throughout the whole design flow starting from input control and data flow characteristics of the application and ending with FPGA implementation data. The analysis of the design flow showed dependence of final implementation on datapath structure and its components complexities.