Dany Minier

Source-synchronous testing of multilane PCI Express and HyperTransport buses

This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses. This approach is suitable for integration with existing ATE and can provide more than 100 independent differential-pair signals. We describe a specific application with 32 lanes of PCI Express, running at 2.5 gigabits per second (Gbps) per lane, and 32 data channels of HyperTransport, at 1.6 Gbps per channel. The differential source-synchronous nature of these buses presents difficulties for traditional (single-ended, synchronous) ATE. We solve these problems by using true-differential driver and receiver test modules tailored for the specific I/O protocols. We satisfy a further requirement for jitter tolerance testing by incorporating a novel digitally synthesized jitter injection technique in the driver modules. The modular nature of our approach permits customization of the test system hardware and optimization for specific DUT test requirements.

A development platform and electronic modules for automated test up to 20 Gbps

An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called “Data Vortex” operating at 2.5Gbps on each of 18 channels (≫40Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.

Multi-GHz loopback testing using MEMs switches and SiGe logic

This paper demonstrates the application of micro-electromechanical switches (MEMs) and SiGe logic devices for passive and active loopback testing of wide data buses at rates up to 6.4Gbps per signal. Target applications include HyperTransport, Fully-Buffered DIMM, and PCIexpress, among others. Recently-commercialized MEMs technology provides high bandwidth (>7GHz) in very small packages in order to support wide parallel buses. SiGe logic also supports >7 Gbps signals when active shaping of the waveform is required. Loopback modules are described with between 9 and 16 differential channels. Multiple cards handle very wide buses or multiple ports. Passive cards utilize MEMs for switching between the Loopback (self-test) mode and traditional ATE source/receiver channels (which are also used for DC parametric tests). It is this switching function that benefits from the MEMs increased density. Active loopback cards provide additional waveform-shaping functions, such as buffering, amplitude attenuation or modulation, deskew, delay adjustment, jitter injection, etc. The modular approach permits pre-calibration of the loopback electronics, and easy reconfiguration between design validation, characterization testing, and high-volume production testing.

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test

A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. It is intended to extend the capabilities of an existing 6.4 Gbps ATE, serving as a plug-in module in an active device interface board (DIB). This prototype circuit provides (1) direct connections to ATE channels for DC parametrics and low-speed functional testing, (2) 2:1 multiplexing of 6.4 Gbps to produce 12.8 Gbps stimuli with picosecond deskew, jitter-injection, and amplitude adjustment, (3) 1:2 fanout of 12.8 Gbps DUT response signals to allow testing by two 6.4 Gbps ATE channels, (4) full-rate low-jitter active loopback path with amplitude adjustment, and (5) auxiliary outputs for parallel monitoring of both transmitted and received signals. The basic logical structure is presented, and features of the module construction are described. A novel high-bandwidth adjustable delay circuit is described, that is used for deskew and XOR-based multiplexing. The performance of the module is demonstrated between 5.0 Gbps and 12.8 Gbps.

Multiplexing ATE channels for production testing at 2.5 Gbps

We describe two versions of a multiplexing test system for multigigahertz devices. Our approach leverages test resources available in existing ATE, and achieves higher rates with added multiplexing logic. In the prototype, 32 high-speed differential-pair signals each support data at 2 Gbps to 2.5 Gbps. An updated system uses water cooling to better maintain the test electronics temperature. This system also has improved relays for better signal integrity, and better embedded calibration circuits to obtain stable operation at 2.5 Gbps. The production version is scalable to as many as 144 high-speed differential-pair signals. Integral to the design are embedded circuits that support automated, accurate timing calibration with 10-ps resolution.

Method for reducing jitter in multi-gigahertz ATE

Controlling jitter on a picosecond (or smaller) time scale has become one of the most difficult challenges for testing multi-gigahertz systems. In this paper we present a novel method for reducing jitter in timing-critical ATE signals. This method uses a real-time averaging approach to combine multiple ATE signals and produces timing references with significantly lower random jitter. For example, we demonstrate a 3times reduction in jitter by combining eight ATE signals (each with sigma=4ps) to produce a low-jitter signal (sigma=1.3ps). The measured jitter reduction is shown to closely match that predicted by theory. This counter-intuitive (but welcome) result is of general interest for the design of any low-jitter system, and is particularly helpful for multi-GHz ATE where precise timing is so critical

MEMS switches and SiGe logic for multi-GHz loopback testing

We describe the use of microelectromechanical system (MEMS) switches and SiGe logic devices for both passive and active loopback testing of wide data buses at rates up to 6.4 Gbps per signal. Target applications include HyperTransport, fully buffered DIMM, and PCI Express, among others. Recently introduced MEMS devices provide >7GHz bandwidth in a very small package (needed to handle wide buses). SiGe logic supports >7Gbps signals when active shaping of the waveform is required. Each loopback module typically supports between 9 and 16 differential channels. Multiple cards are used to handle applications with very wide buses or multiple ports. Passive cards utilize MEMS for switching between the loopback (self-test) mode and traditional automated test equipment (ATE) source/receiver channels. Future active card designs may provide additional waveform-shaping functions, such as buffering, amplitude attenuation/modulation, deskew, delay adjustment, jitter injection, and so forth. The modular approach permits precalibration of the loopback electronics and easy reconfiguration between debug or characterization testing and high-volume production screening.

Demonstration of 20 Gbps digital test signal synthesis using SiGe and InP logic

This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been proven for lower-speed (i.e. ≤12.8Gbps) applications [1–3]. But its success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost components are selected so that the method can be applied to test scenarios requiring many high-speed channels. Careful analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method.

Picosecond delay adjustment for 12.8 Gbps multiplexed testing

A novel high-bandwidth adjustable delay circuit is described that is used for XOR-based multiplexing of multi-Gbps test signals. By precisely-aligning the phase offset of two 6.4 Gbps ATE signals, an Indium-Phosphide exclusive-OR gate is used to synthesize a double-data-rate signal with picosecond resolution and ~30 ps accuracy. The delay circuit is based on an experimentally-observed second-order effect in a SiGe variable-amplitude differential buffer. A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. The performance of the module is demonstrated between 6.4 Gbps and 12.8 Gbps.