David C. Keezer

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

Constant Current Power Transmission Line-Based Power Delivery Network for Single-Ended Signaling

The performance of a system depends heavily on the communication speed between integrated circuits. One of the most important bottlenecks that limit the communication speed is simultaneous switching noise (SSN). A major contribution to SSN is return path discontinuities, which are caused by the change or disruption in return currents due to via transitions, aperture effects, etc. In this paper, a new concept based on power transmission line (PTL) is proposed to supply power, improve signal and power integrity, and enhance chip-to-chip communication speed. The first demonstration of constant current PTL (CCPTL)-based single-ended signaling scheme is implemented and measured. The results show that the CCPTL scheme improves the quality of the received signal in terms of voltage and timing margin.

Terabit-per-second automated digital testing

This paper describes a test application for an IC with over 200 logic signals each carrying multiple-gigahertz data. An aggregate data rate approaching a terabit-per-second is attained during the test. A high pin-count automated test system with a maximum frequency of 1.33 Gbps DNRZ is used as a development platform. Data rate tripling logic is added to the system to produce stimuli signals each with DNRZ rates up to 4 Gbps. High-speed sampling circuits are added to capture the device output signals at these same frequencies. Several example measurements illustrate the signal quality that is achieved. The extraordinary performance exhibited by this application represents one of the most challenging digital test applications reported to-date, and foreshadows expectations for future automated test equipment.

REAL-TIME DATA COMPARISON FOR GIGAHERTZ DIGITAL TEST

A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.

Modular extension of ATE to 5 Gbps

Existing digital automated test equipment (ATE) can provide signals at about 1 Gbps or slightly higher. To accommodate multi-GHz test needs, some ATE provide options for a few faster channels (up to 3.6 Gbps). However, leading-edge parts may require 100s of these signals and in some cases at even higher speeds (5 and 10 Gbps). This work describes a modular approach that allows for as many as 144 multiplexing and/or sampling channels to be added to existing ATE. The modules developed, so far include multiplexers, demultiplexers, and high-speed samplers that each support multiple high-speed differential signals. Production units operating up to 2.5 Gbps were introduced. We provide more detailed characterization of these modules and describe new modules targeting 3.2 Gbps and 5.0 Gbps applications. Various re-clocking techniques and proprietary calibration methods are used in order to reduce timing errors (especially jitter) to the sub-50ps range. The general system configuration, and key features of the newly developed modules are presented.

Bit-parallel message exchange and data recovery in optical packet switched interconnection networks

Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.

Application and demonstration of a digital test core: optoelectronic test bed and wafer-level prober

Abstract A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of programmable I/O for testing circuits and systems. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. This technique has been expanded upon to produce greater functionality at higher frequencies. Based upon limitations of current ATE and BIST, the need for the digital test core is described. The test core concept is reviewed within an opto-electronic pattern generator and sampler with an eventual goal of terabit-per-second aggregate data rate. The performance of the device is discussed, and a second application of the digital test core is introduced as a nano-scale wafer-level embedded tester.

Source-synchronous testing of multilane PCI Express and HyperTransport buses

This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses. This approach is suitable for integration with existing ATE and can provide more than 100 independent differential-pair signals. We describe a specific application with 32 lanes of PCI Express, running at 2.5 gigabits per second (Gbps) per lane, and 32 data channels of HyperTransport, at 1.6 Gbps per channel. The differential source-synchronous nature of these buses presents difficulties for traditional (single-ended, synchronous) ATE. We solve these problems by using true-differential driver and receiver test modules tailored for the specific I/O protocols. We satisfy a further requirement for jitter tolerance testing by incorporating a novel digitally synthesized jitter injection technique in the driver modules. The modular nature of our approach permits customization of the test system hardware and optimization for specific DUT test requirements.

Multi-purpose digital test core utilizing programmable logic

A general-purpose, reconfigurable logic circuit, including an FPGA and a standard USB communications port, is introduced to implement many of the functions of traditional automated test equipment (ATE). An optional port to local memory is included for applications requiring extensive test vector storage. The test core provides a substantial number of programmable I/Os for testing other circuits. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. Based upon limitations of current BIST and ATE, the need for the digital test core is described. The test core concept is introduced, and a specific circuit design is presented. This design is first evaluated independently and is then embedded into two example applications, including: (1) a high speed transmitter/receiver, and (2) a continuity checker for high-density flip-chips.

Low cost ATE pin electronics for multigigabit-per-second at-speed test

This paper describes the design and performance of low-cost electronics modules which can be used for testing multigigabit-per-second digital components and subsystems within an automated test environment. Pattern stimuli are generated at rates up to 2.67 Gbps with timing errors less than 50 ps. Pattern sensitivity is less than 40 ps and RMS jitter is typically about 8 ps. A high-speed differential buffer provides emitter-coupled logic (ECL) transitions in about 200 ps. A data-capture circuit is shown to sample repetitive waveforms with 2.67 Gbps data rates. It is estimated that the component cost per channel for a large ATE would be under