Danyan Zhang

Neuron-MOS-based Dynamic Circuits for Multiple-Valued Logic

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing and low propagation delay. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology. For comparison, the energy consumption and the output delay of the proposed circuits are measured during the simulations.

Dynamic Quaternary Circuit with Neuron-MOS Transistor

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing, low propagation delay and no static power consumption. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Novel differential logic using floating-gate MOS transistors

A new static CMOS differential logic based on multiple-input floating-gate MOS (FGMOS) transistor is proposed. In this circuit configuration, a pair of n-channel multiple-input FGMOS pull down networks is used to replace the nMOS logic tree in the conventional cascode voltage switch logic (CVSL) circuit in order to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. On the basis of the proposed synthesis method, some logic circuits including full adder are designed. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology with a power supply of 1.5V is utilized to validate the effectiveness of the proposed logic circuits.

Dynamic Ternary Logic Gate Using Neuron-MOS Literal Circuit and Double Pass-Transistor Logic

A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary and dual circuits using double pass-transistor are also presented. The design results of dynamic ternary AND/NAND, OR/NOR, and mod-3 multiplication gate, demonstrate the effectiveness of the proposed scheme. The benefit of the proposed voltage-mode dynamic ternary gates is that they can be fabricated by standard CMOS process with a 2-ploy layer. Besides, they have simple and perfectly symmetrical structure. The effectiveness of the proposed dynamic ternary gates has been validated by HSPICE simulation results with TSMC 0.35µm 2-ploy 4-metal CMOS technology.

NORA circuit design using neuron-MOS transistors

A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel neuron-MOS logic block by employing summation signal is discussed. HSPICE simulation results using TSMC 0.35μm 2-ploy 4-metal CMOS process with 1.5V power supply, have verified the effectiveness of the proposed neuron-MOS-based NORA circuits. For comparison, the power consumption and the output delay of the proposed NORA adders are measured during the simulations.

A true single-phase clocked full-adder using floating-gate MOS transistor

A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using FGMOS transistors, the circuit structure can be dramatically simplified. Since the voltage signals are easy to be added by means of floating gate in FGMOS transistor, a summation signal treated as a medium variable is employed in the circuit design. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits. For comparison, the power consumption and the output delay of the proposed TSPC full-adder are measured during the simulations.

Novel Differential Flip-Flops Using Neuron-MOS Transistors

Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch double edge-triggered(IL-DET) flip-flop. In the new differential flip-flops, a pair of n-channel neuron-MOS transistors is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by employing the neuron-MOS transistors. In the proposed configurations, the edge-triggering operations are achieved by a narrow pulse produced by two input gates of multiple-input neuron-MOS transistors receiving a clock and a delayed clock, respectively. In comparison with neuron-MOS-based differential master-slave flip-flop, the IL-SET configuration has reduced transistor count and lower power consumption. The HSPICE simulation using TSMC 0.35μm 2-ploy 4-metal CMOS technology validated the effectiveness of the proposed approach.

An Enhanced Dynamic Switch Logic with Floating-Gate MOS Transistors

A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically simplified by utilizing multiple-input FGMOS transistors. The proposed dynamic logic does not require complementary inputs, and keeps the benefits of EDCVSL. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is given. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits.

Design of Ternary D Flip-Flop Using One Latch with Neuron-MOS Literal Circuit

A novel CMOS ternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The ternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode ternary flip-flop is that can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported ternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35µm 2-ploy 4-metal CMOS technology. The proposed construction can be easily extended to the design of multiple-valued edge-triggered flip-flop with a higher radix.

Novel asymmetric 8T SRAM cell with dynamic power

Data stability, power consumption and delay are important issues with the scaling of CMOS technology. An asymmetric eight-transistor SRAM cell with improved static-noise margin (SNM) is proposed. In this new 8T SRAM cell, unilateral reading mechanism and dynamic power scheme are combined. Results are validated by HSPICE simulation using 45nm PTM model. The simulated results of the SNM, the power consumption, the propagation delay and the power delay product (PDP) are compared between the dynamic power 6T SRAM cell and the proposed 8T SRAM cell.