Guoqiang Hang

Quaternary edge-triggered flip-flop with neuron-MOS literal circuit

A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode quaternary flip-flop is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported quaternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Power optimization for VLSI circuits and systems

Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture level.

Design of dynamic ternary logic using floating-gate MOS transistor

A new dynamic circuit scheme to realize voltage-mode ternary circuit using floating-gate MOS (FGMOS) transistor is presented. The dynamic ternary inverter and literal circuits with the less complex structure are designed, and they can be implemented by the standard CMOS process with a double-poly layer without any modification of the thresholds. In the proposed scheme, the circuit output is always brought to logic 1 during the pre-charge phase, to avoid charge sharing in cascaded gates, and then the disadvantage of buffering between stages is eliminated. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Neuron-MOS-based Dynamic Circuits for Multiple-Valued Logic

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing and low propagation delay. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology. For comparison, the energy consumption and the output delay of the proposed circuits are measured during the simulations.

A clocked differential switch logic using floating-gate MOS transistors

A novel differential dynamic CMOS logic using multiple-input floating-gate MOS(FGMOS) transistors is proposed. In this circuit family, a pair of n-channel multiple-input FGMOS pull down logic networks is used to replace the nMOS logic tree in the conventional dynamic differential cascode voltage switch logic circuit. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. By using multiple-input FGMOS, the logic tree can be significantly simplified. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed design scheme.

Dynamic Quaternary Circuit with Neuron-MOS Transistor

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing, low propagation delay and no static power consumption. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors

Novel differential flip-flops using neuron-MOS transistors are presented, including single edge-triggered flipflop and double edge-triggered flip-flop. In the new differential flip-flops, a pair of n-channel multiple-input neuron-MOS pull down logic networks is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by employing the multiple-input neuron-MOS transistors. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed design scheme. The simulated results of propagation delay and power dissipation are also given.

Adjustable Schmitt triggers using floating-gate MOS transistors

Novel Schmitt triggers based on multiple-input floating-gate MOS(FGMOS) transistors are presented. By using the control signal of multiple-input gate, the adjustable threshold voltages can be achieved conveniently. As the variable threshold voltage can be achieved easily in FGMOS circuit, all the proposed Schmitt triggers have considerable simpler structure. The effectiveness of the proposed Schmitt triggers has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.

Dynamic Ternary Logic Gate Using Neuron-MOS Literal Circuit and Double Pass-Transistor Logic

A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary and dual circuits using double pass-transistor are also presented. The design results of dynamic ternary AND/NAND, OR/NOR, and mod-3 multiplication gate, demonstrate the effectiveness of the proposed scheme. The benefit of the proposed voltage-mode dynamic ternary gates is that they can be fabricated by standard CMOS process with a 2-ploy layer. Besides, they have simple and perfectly symmetrical structure. The effectiveness of the proposed dynamic ternary gates has been validated by HSPICE simulation results with TSMC 0.35µm 2-ploy 4-metal CMOS technology.

A new schmitt trigger with n-channel neuron-MOS transistor

A new structure of voltage-mode binary Schmitt trigger with n-channel neuron-MOS device is designed. In this presented circuit scheme, the hysteresis window of the Schmitt circuit can be shifted by adjusting the value of the external control signal, and the hysteresis voltage can be verified by choosing the different ratio of capacitive coupling coefficients. Besides, the proposed Schmitt circuit has a simpler structure, in which only one n-channel neuron-MOS transistor, a pMOS transistor and one conventional CMOS inverter are required. Using HSPICE program and TSMC 0.35μm 2-ploy 4-metal CMOS process parameters, the effectiveness of the proposed neuron-MOS-based Schmitt trigger is validated. The threshold and hysteresis voltages are measured during simulation.