Danyu Wu

A 6GHz direct digital synthesizer MMIC with nonlinear DAC and wave correction ROM

This paper proposes a new DDS architecture combined with Nonlinear DAC and Wave-Correction-ROM (WCR) which shows both high operating speed and accuracy. Based on this architecture, a 6GHz 8-bit DDS MMIC is designed and fabricated in 60GHz GaAs HBT Technology. The DDS MMIC includes 8-bit pipeline accumulator, an 8×8×3bits WCR, two combined DACs and an analog Gilbert Cell for sine-wave generation with 8-bit amplitude resolution. The DDS chip is tested in on-wafer measurement system. The measured spurious free dynamic range (SFDR) is 33.96dBc with 2.367GHz output under a 6GHz maximum clock (FCW=0×65). It shows an average SFDR of 37.5dBc and the worst case SFDR of 31.4dBc (FCW=0×70) within the whole Nyquist band under a 5GHz clock frequency. The whole chip occupies 2.4×2mm2 of area consuming 3.27W of power from a single −4.6Vpower supply.

A 10GHz 8-bit Direct Digital Synthesizer implemented in GaAs HBT technology

This paper presents a 10GHz 8-bit Direct Digital Synthesizer (DDS) Microwave Monolithic Integrated Circuit (MMIC) implemented in 1µm GaAs HBT technology. The DDS takes a Double-Edge-Trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC based ROM-less architecture, that can maximize the utilization ratio of GaAs HBTs high-speed potential. With an output frequency up to 5GHz, the DDS gives an average Spurious Free Dynamic Range (SFDR) of 23.24dBc through the first Nyquist band, and consumes 2.4W of DC power from a single −4.6V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4×2.0mm2.

Novel high efficiency broadband Ku band power combiner

High power solid-state power amplifiers require a high efficiency power dividing/combining structure to keep the power loss as low as possible. The heat sinking capability of the divider/combiner also limits its maximum output power with continues wave (CW) configuration. In this paper, we introduce a novel 8-way Ku band power divider/combiner system, it demonstrate advantages of low loss, broadband and good heat sinking capability simultaneously. As its sub-components, low loss probes for waveguide-to-microstrip transition and low loss broadband 1-to-2 power combiners are designed and fabricated. The measured back-to-back insertion loss of the whole 8-way power combiner is lower than 0.5dB in the whole Ku band, and the corresponding combining efficiency is as high as 94.5%. The simulated thermal resistance of the system is as low as 0.21°C/W, indicating the proposed power combiner is able to produce 50W of CW output power with commercial available Monolithic Microwave Integrated Circuits (MMICs).

An ultra-high-speed direct digital synthesizer MMIC

This paper presents an ultra-high-speed direct digital frequency synthesizer (DDS) microwave monolithic integrated circuit (MMIC) implemented in 1μm GaAs HBT technology. The DDS has the capabilities of direct frequency modulations with 8-bit frequency resolutions. Utilizing a Double-Edge-Trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC based ROM-less architecture, this DDS MMIC can maximize the utilization ratio of GaAs HBTs high-speed potential. With an external clock output frequency of 5GHz, the DDS can output sine signal of up to 5GHz frequency giving an average Spurious Free Dynamic Range (SFDR) of 23.24dBc through the first Nyquist band. The DDS MMIC consumes 2.4W of DC power from a single −4.6V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4×2.0mm2.

A 30GS/s 6bit SiGe ADC with input bandwidth over 18GHz and full data rate interface

In this paper, a time-interleaved 30GS/s 6bit ADC fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. A bandwidth boosting technique and packaging solution has been proposed which enables the ADC to achieve input bandwidth over 18GHz. A full data rate interface is integrated to transmit all the data in real time. The ADC has a SFDR >35dBc over the entire Nyquist frequency. An effective number of bits (ENOB) above 5.0 are achieved for low frequency input tones, dropping to 3.5 at 16GHz.

A Combined Model With Electrothermal Coupling and Electromagnetic Simulation for Microwave Multifinger InP-Based DHBTs

This paper presents a combined model with electrothermal coupling and electromagnetic (EM) simulation for multifinger InP-based double heterojunction bipolar transistors (DHBTs). The electrothermal coupling effect, which occurs in multifinger InP DHBTs, is characterized based on 3-D thermal simulation. In addition, EM simulation technique is presented to account for the distributed effect of interconnection of the fingers and their surroundings. A large-signal model for single-finger DHBTs is implemented as a seven-port symbolically defined device, which accounts for several physical phenomena, including the self-heating effect, Kirk effect, current blocking effect, mobile charge modulation of the base-collector capacitance, and velocity field modulation in the transit time. The combined model implemented in Agilent-ADS is verified by comparing the simulated and measured data in dc small-signal S-parameters and large-signal microwave power characteristic. This approach allows a simple method to analyze and predict microwave multifinger InP DHBTs for power amplifier circuit design using commonly available computer-aided design tools such as Agilent-ADS.

A 4GS/s 8bit ADC fabricated in 0.35µm SiGe BiCMOS technology

In this paper, a low cost 4GS/s 8bit Folding-and-Interpolation (F&I) ADC has been demonstrated. To avoid threshold-mismatch and delay-mismatch between coarse and fine quantizer, a novel coarse quantizer with analog pre-processing circuits are proposed. According to the measurement result, the proposed coarse quantizer has successfully eliminated the glitch code. The ADC is capable of sampling analog input frequencies up to 1.5GHz with greater than 7.0 effective number of bits (ENOB) performance. The ADC has a die size of 3.8×3.8 mm2 and consumes 4.1W of power.

Design of a 10GHz bandwidth variable gain amplifier using a GaAs HBT technology

This paper reports a fully differential variable gain amplifier (VGA) using GaAs heterojunction bipolar transistors (HBTs). Gilbert cells with transimpedance loads are applied to achieve wide bandwidth. According to the single-ended measurements, the 3-dB bandwidth is 10.5GHz at a maximum gain of 22dB. A gain-bandwidth product of 132GHz is achieved. The circuit consists of two cascaded variable gain stages to offer a high dynamic range. The experiment results show the dynamic range is larger than 28dB. The chip consumes 368mV at a supply voltage of -5.2V. Design considerations and experimental results are presented in this paper.

A wide dynamic range transimpedance amplifier with high gain-bandwidth product for 10 Gb/s optical links

This paper presents the design method and implementation of a wide dynamic range transimpedance amplifier (TIA) with high gain-bandwidth product (GBW) based on 1μm GaAs process of WIN company. The wide dynamic range results from the utilization of a parallel feedback structure that divides the input current when it is large. And the high GBW owes to the limiting amplifier (LA) which functions as a gain stage based on a modified Cherry-Hopper amplifier. The proposed TIA achieves a maximum input current of 3.5 mA and a transimpedance of 68.6 dBΩ and a bandwidth of 10.9 GHz.

A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC

Ultra high speed and moderate resolution ADCs with low latency are demanded in many applications. A 4-GS/s 8-bit ADC is implemented in the 0.35 μm SiGe BiCMOS technology. It is based on the two-channel time-interleaved architecture and each sub-ADC employs the two-stage cascaded folding and interpolating topology which guarantees the low-latency property. Calibration circuits are introduced to compensate for the mismatch between the two sub-ADCs. The whole chip area is about 4.0 × 4.0 (mm2). The ADC exhibits DNL of 0.26/−0.34 LSB and INL of 0.96/−0.92 LSB. The ENOB is 7.1 bits and the SFDR is about 56 dB at 10.1 MHz input. The SNDR is above 42 dB over the first and the second Nyquist zone. The SFDR is above 45 dB over the first Nyquist zone and the second Nyquist zone. The ERBW is about 1.4 GHz.