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Daren Eugene Streett

Qualcomm

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Publication

Featured researches published by Daren Eugene Streett.

Archive | 2007

Virtually-Tagged Instruction Cache with Physically-Tagged Behavior

Thomas Andrew Sartorius; Rodney Wayne Smith; Daren Eugene Streett

Archive | 2009

Apparatus and methods for speculative interrupt vector prefetching

Daren Eugene Streett; Brian Michael Stempel

Archive | 2006

Debug circuit comparing processor instruction set operating mode

Kevin Charles Burke; Brian Michael Stempel; Daren Eugene Streett; Kevin Allen Sapp; Leslie Mark Debruyne; Nabil Amir Rizk; Thomas Andrew Sartorius; Rodney Wayne Smith

Archive | 2014

ELIMINATING REDUNDANT SYNCHRONIZATION BARRIERS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA

Melinda J. Brown; James Norris Dieffenderfer; Michael Scott McIlvaine; Brian Michael Stempel; Daren Eugene Streett

Archive | 2016

MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION

Vimal K. Reddy; Niket Kumar Choundhary; Michael Scott McIlvaine; Daren Eugene Streett; Robert Douglas Clancy; James Norris Dieffenderfer; Michael William Morrow

Archive | 2014

Qualifying Software Branch-Target Hints with Hardware-Based Predictions

Michael William Morrow; James Norris Dieffenderfer; Thomas Andrew Sartorius; Michael Scott McIlvaine; Brian Michael Stempel; Daren Eugene Streett; Vimal K. Reddy

Archive | 2014

OPTIMIZING PERFORMANCE FOR CONTEXT-DEPENDENT INSTRUCTIONS

Daren Eugene Streett; Brian Michael Stempel; Thomas Philip Speier; Rodney Wayne Smith; Michael Scott McIlvaine; Kenneth Alan Dockser; James Norris Dieffenderfer

Archive | 2013

Establishing a branch target instruction cache (btic) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

James Norris Dieffenderfer; Michael William Morrow; Michael Scott McIlvaine; Daren Eugene Streett; Vimal K. Reddy; Brian Michael Stempel

Archive | 2012

Multi Level Indirect Predictor using Confidence Counter and Program Counter Address Filter Scheme

Kulin Narendra Kothari; Michael William Morrow; James Norris Dieffenderfer; Michael Scott McIlvaine; Brian Michael Stempel; Daren Eugene Streett

Archive | 2015

Branch target instruction cache (btic) to store a conditional branch instruction

Niket Kumar Choudhary; Michael Scott McIlvaine; Daren Eugene Streett; Vimal K. Reddy; Shekhar Srikantaiah; Sandeep Navada; Robert Douglas Clancy; James Norris Dieffenderfer; Thomas Andrew Sartorius

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Collaboration

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Brian Michael Stempel

IBM

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Michael Scott McIlvaine

Qualcomm

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James Norris Dieffenderfer

Qualcomm

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Michael William Morrow

Qualcomm

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Rodney Wayne Smith

IBM

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Thomas Andrew Sartorius

IBM

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Vimal K. Reddy

Qualcomm

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Kevin Allen Sapp

Qualcomm

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Kevin Charles Burke

Qualcomm

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Leslie Mark Debruyne

Qualcomm

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