Dariusz Pienkowski

Reconfigurable receiver approach for 4G terminals and beyond

An overview on RF-front-end architectures and technologies for future reconfigurable mobile communication systems (4G-systems) is given. Favourable standard combinations are WCDMA and WLAN. RF front-end key components like low noise amplifiers, mixers, synthesizers and baseband variable gain amplifiers are treated, particularly with regard to reconfigurable systems.

Resistive MOSFET mixer for mobile direct conversion receivers

A double balanced resistive MOSFET mixer developed for mobile communication terminals of the forth generation will be presented in this paper. Receivers of such systems have to be compatible to different standards and different down-conversion methods with the same hardware. Hence, it can be used also as IQ demodulator for RF and IF signals, depending on the front-end architecture used. RF and IF frequency ranges are 2-3 GHz and DC to 50 MHz, respectively. The mixer consumes no DC power, has low LO power consumption, a high linearity, and low RF noise. No 1/f- noise could be detected in the IFfrequency range down to 10 kHz. A conversion loss of 6 to 6.5 dB has been achieved. Measured linearity values are +7 dBm for 1dB power compression and 16.5 dBm for third order intercept point. All isolation values are typically higher than 45 dB between all ports. The circuit was simulated using ADS from Agilent and the layout work has been carried out in Cadence. We will discuss the design flow in this paper and present a comparison of simulated and measured results. In comparison with reported results on 0.35 /spl mu/m MOSFET mixers, we will show that the measured mixer data are excellent regarding the low-frequency noise, DC power consumption, linearity, bandwidth and isolation. The complete set of features makes this mixer type a well suitable candidate for 4G mobile communication receivers.

Integrated 130 nm CMOS passive mixer for 5 GHz WLAN applications

An integrated 130 nm CMOS mixer for 5 GHz WLAN applications is proposed. A resistive double balanced concept has been chosen as part of a half RF super-heterodyne receiver architecture. The mixer provides a conversion loss of 5 dB, a SSB noise figure of less than 8 dB, an IIP3 of 10 dBm and a LO-RF isolation of more than 45 dB. The circuit dissipates no DC power and no drain bias supply is necessary. The entirety of properties makes this circuit very favorable for all wireless applications.

A 2.14 GHz, 0.78 dB noise figure CMOS low noise amplifier

This work presents a 2 GHz LNA designed for UMTS mobile terminals. The circuit is implemented in a 0.13 mum CMOS technology. In design methodology small signal and noise parameters of the amplifier are combined, and pad capacitance is used for improving the noise performance. The designed amplifier shows 0.78 dB noise figure and 12 dB gain at 2.14 GHz for 3.5 mA supply current and 1.2 V supply voltage

Double balanced resistive mixer for mobile applications

We present a double balanced resistive mixer for mobile applications using a 0.35 /spl mu/m MOSFET technology. The mixer has been designed for direct conversion receivers, with RF- and IF-frequency ranges of 2-3 GHz and DC to 50 MHz, respectively. Excellent performance has been achieved. Typical values are 6 dB conversion loss, 6.5 dB noise figure, 7 dBm 1 dB power compression, 16 dBm third order intercept point, and 50 dB isolation between all ports. The mixer does not consume DC-power and the needed LO-voltage amplitude is 1 V typical. No low frequency noise was detectable down to 10 kHz. We report on the design strategy and present simulated and measured results.

Efficient design of multituned transmission line NMR probes: The electrical engineering approach

Transmission line-based multi-channel solid state NMR probes have many advantages regarding the cost of construction, number of RF-channels, and achievable RF-power levels. Nevertheless, these probes are only rarely employed in solid state-NMR-labs, mainly owing to the difficult experimental determination of the necessary RF-parameters. Here, the efficient design of multi-channel solid state MAS-NMR probes employing transmission line theory and modern techniques of electrical engineering is presented. As technical realization a five-channel ((1)H, (31)P, (13)C, (2)H and (15)N) probe for operation at 7 Tesla is described. This very cost efficient design goal is a multi port single coil transmission line probe based on the design developed by Schaefer and McKay. The electrical performance of the probe is determined by measuring of Scattering matrix parameters (S-parameters) in particular input/output ports. These parameters are compared to the calculated parameters of the design employing the S-matrix formalism. It is shown that the S-matrix formalism provides an excellent tool for examination of transmission line probes and thus the tool for a rational design of these probes. On the other hand, the resulting design provides excellent electrical performance. From a point of view of Nuclear Magnetic Resonance (NMR), calibration spectra of particular ports (channels) are of great importance. The estimation of the π/2 pulses length for all five NMR channels is presented.

22 GHz amplifier using a 0.12 μm CMOS technology

A 22 GHz low-noise amplifier (LNA) was designed, fabricated in standard 0.12 μm CMOS technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure of 10.3 dB and return losses at in-/output of 15 and 10 dB, respectively. The LNA operates at a supply voltage 1.2 V and consumes a DC-power of just 5.4 mW. To the author best knowledge it is the first cascode implementation in CMOS standard process beyond 20 GHz.

A 0.7 V, 23 GHz, low cost BiCMOS amplifier with 2.8 mW power consumption

This paper shows a fully integrated, ESD protected, low-power, low-voltage amplifier designed with a low-cost 0.18 mum SiGe technology. The amplifier achieves 11 dB gain, 8 dB noise figure at 23 GHz and 1 dB compression point of -18 dBm consuming 2.8 mW from the 0.7 V supply voltage. At this frequency the amplifier shows also 9 and 13 dB input and output return losses, respectively. Gain and power consumption results yield to a gain per power-supply figure of merit of 3.9 dB/mW, which is one of the highest reported for that frequency range

2 GHz, 130 nm CMOS low noise amplifier for WCDMA

This work presents a 2 GHz LNA designed for WCDMA mobiles. The circuit is implemented in a 0.13 /spl mu/m CMOS technology. The design methodology is presented taking into consideration the influence of the pad capacitance on noise behaviour. The equivalent noise resistance can be lowered by this way. The designed amplifier shows 0.78 dB noise figure and 12 dB gain at 2.14 GHz for 3.5 mA supply current and 1.2 V supply voltage.

Resistive mixers for reconfigurable wireless front-ends

Two resistive mixers realized in a 0.13 /spl mu/m CMOS process are presented. The mixers are designed for implementation in a reconfigurable mobile terminal that supports the WCDMA mobile phone standard and the IEEE 802.11a and HIPERLAN/2 WLAN standards, respectively. The mixer design process, as well as simulated and measured results, are given and discussed. The entirety of properties and performance makes these mixer types very attractive for reconfigurable architectures.