Darrell D. Boggs

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

The processor has an execution unit with high bandwidth capability and low average instruction latency. The processor pipeline includes an Execution Trace Cache, Renamer, Scheduler, register file and execution unit. IA32 instructions are decoded when they are fetched from the L2 cache after a miss in the Execution Trace Cache. Serving as the primary instruction cache, the Execution Trace cache stores decoded instructions to remove the long delay for decoding IA32 instructions from this path, reducing the branch missprediction loop. Instruction traces follow the predicted execution path, not sequential instruction addresses. While this pipeline supplies the high bandwidth work stream, the length of this pipe contributes to instruction latency only when there is a branch miss-prediction (roughly once in 100 instructions).