Michael Upton

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

The processor has an execution unit with high bandwidth capability and low average instruction latency. The processor pipeline includes an Execution Trace Cache, Renamer, Scheduler, register file and execution unit. IA32 instructions are decoded when they are fetched from the L2 cache after a miss in the Execution Trace Cache. Serving as the primary instruction cache, the Execution Trace cache stores decoded instructions to remove the long delay for decoding IA32 instructions from this path, reducing the branch missprediction loop. Instruction traces follow the predicted execution path, not sequential instruction addresses. While this pipeline supplies the high bandwidth work stream, the length of this pipe contributes to instruction latency only when there is a branch miss-prediction (roughly once in 100 instructions).

Resource allocation in a high clock rate microprocessor

This paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.

A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus

Several architectural innovations intended to reduce access latency and improve overall throughput increase system bandwidth requirements. Bandwidth scales with clock speed, and can be regarded as an architectural resource to be applied to latency reduction. A properly designed bus provides low arbitration latency and delivers high sustained bandwidth. The paper evaluates the performance of 3.2 Gbyte/s peak bandwidth, low-latency arbitration bus connecting a GaAs superscalar CPU to a GaAs memory management unit. A microarchitectural performance model was written in the Verilog hardware description language. Bus transactions characteristic of the SPECint92 benchmarks and other workloads were generated as input. Sustained bandwidths of 1.68 Gbytes/s were achieved with arbitration costs of less than 0.5 cycles per data transfer. >

Gallium-arsenide process evaluation based on a RISC microprocessor example

The authors evaluate the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivities of the microprocessor and other large circuit blocks to different process parameters are analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance. >

GaAs RISC processors

A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz.<<ETX>>

A 160000 transistor GaAs microprocessor

Describes a single-chip GaAs microprocessor that includes a Ling-adder-based ALU (arithmetic and logic unit), a 32-bit shifter, a 32-word register file, a 4-word write buffer, a 32-word on-chip instruction cache, support for 2 levels of off-chip instruction and data caches, and an asynchronous system interface. It uses direct-coupled FET logic and integrates 160000 transistors on a 13.9-mm*7.8-mm die. When operating from a 2-V supply, the chip typically dissipates 24 W. Portions of the chip operate at 200 MHz. Full functionality is verified at 100 MHz.<<ETX>>

A variable-voltage bidirectional I/O pad for digital GaAs applications

A bidirectional I/O pad for digital GaAs applications has been designed, fabricated, and tested using Vitesse Semiconductor process technology. The I/O pad is designed to operate at frequencies up to 500 MHz and at GTL, ECL, or Rambus voltage levels. The I/O pads can be calibrated to these voltage levels either manually using external signals or internally using on-chip digital calibration logic.