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Dive into the research topics where Darrell Rinerson is active.

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Featured researches published by Darrell Rinerson.


international solid-state circuits conference | 2010

A 0.13µm 64Mb multi-layered conductive metal-oxide memory

Christophe J. Chevallier; Chang Hua Siau; Seow Fong Lim; Sri Rama Namala; Misako Matsuoka; Bruce L. Bateman; Darrell Rinerson

A number of technologies have been proposed to replace NAND Flash as scaling becomes more difficult [1–2]. One promising area includes resistive memories using the conductive metal oxide (CMOx™) technology where multiple memory layers can be stacked [3]. Earlier attempts have been made with non-rewritable materials [4]. The key concepts for a very high density, multi physical layer nonvolatile, rewritable memory have been developed on a 64Mb, 130 nm test chip.


Archive | 2002

Cross point memory array using multiple thin films

Darrell Rinerson; Steven W. Longcor; Edmond R. Ward; Steve Kuo-Ren Hsia; Wayne Kinney; Christophe J. Chevallier


Archive | 2003

Re-writable memory with non-linear memory element

Darrell Rinerson; Christophe J. Chevallier; Steven W. Longcor; Wayne Kinney; Edmond R. Ward; Steve Kuo-Ren Hsia


Archive | 1996

Memory system having programmable control parameters

Frankie F. Roohparvar; Darrell Rinerson; Christophe J. Chevallier; Michael S. Briner


Archive | 2003

Adaptive programming technique for a re-writable conductive memory device

Darrell Rinerson; Christophe J. Chevallier


Archive | 2005

Memory using mixed valence conductive oxides

Darrell Rinerson; Christophe J. Chevallier; Wayne Kinney; Roy Lambertson; Steven W. Longcor; John Sanchez; Lawrence Schloss; Philip F.S. Swab; Edmond R. Ward


Archive | 2003

Non-volatile memory with a single transistor and resistive memory element

Darrell Rinerson; Christophe J. Chevallier; Steven W. Longcor; Wayne Kinney; Edmond R. Ward; Steve Kuo-Ren Hsia


Archive | 2004

Discharge of conductive array lines in fast memory

Christophe J. Chevallier; Darrell Rinerson


Archive | 2002

Cross point memory array using multiple modes of operation

Darrell Rinerson; Christophe J. Chevallier; Steven W. Longcor; Edmond R. Ward; Wayne Kinney; Steve Kuo-Ren Hsia


Archive | 2004

Memory using variable tunnel barrier widths

Darrell Rinerson; Christophe J. Chevallier; Wayne Kinney; Edmond R. Ward

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