Dave Hetzer

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Utilization of spin-on and reactive ion etch critical dimension shrink with double patterning for 32 nm and beyond contact level interconnects

Spin-on chemical shrink, reactive ion etch [RIE] shrink and litho-etch-litho-etch [LELE] double patterning have been utilized to produce dense 90 nm pitch, 26 nm bottom CD contacts starting from 65 nm CD, 126 nm diagonal pitch as printed features. Demonstrated lithographic process window, post etch pattern fidelity, CD, and CD uniformity are all suitable to production. In addition, electrical test results shows a comparable defect a ratio vs. a no chemical shrink baseline.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

Defect detection strategies and process partitioning for SE EUV patterning (Conference Presentation)

The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .

Driving down defect density in composite EUV patterning film stacks

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL. In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

High speed EUV using post processing and self-aligned double patterning as a speed enhancement technique

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Defectivity issues in topcoat-free photoresists

One method being used to reduce the overall lithography process complexity and cost is to utilize a topcoat-less photoresist. Development of these materials utilizes an additive to prevent water penetration and thus forms the same surface property characteristics created by advanced topcoats. The main challenge for topcoat-less resists is increasing the hydrophobicity without causing too much inhibition at the resist surface - which can lead to bridging or residue defects. The key to such a design is in the balance between leaching control versus dissolution characteristics of the resist without disregarding lithography performance and increasing defectivity. The addition of materials into existing ArF photoresists systems have been shown to modulate the contact angle in water-based immersion lithography. The authors have focused this work on the reduction of defects to achieve defectivity levels that are equal or better than existing systems.

Investigation of lithographic feature characteristics using UV cure as a pitch doubling stabilization technology for the 32nm node and beyond

Pitch doubling technologies are necessary for the 32nm half-pitch (HP) and beyond in order to extend optical lithography. Many different techniques have been examined including Litho-Litho-Etch (LLE), Litho-Etch, Litho-Etch (LELE), and Sidewall Image Transfer (SIT). Keeping all of the processes inside the litho cluster, as LLE achieves, affords process simplification and potential for the lowest cost of ownership for pitch doubling. Within LLE alone, there are varying approaches including spin-on chemical freeze materials, thermal cure, UV curable materials, among others. The challenge is to provide robust process performance while still achieving the lowest cost of ownership. For this paper, we are concentrating on the evaluation of the UV cure process. Our findings are the results of optimization of the UV cure dose and bake conditions and its affect on the lithographic performance. The optimized process was investigated for defectivity, critical dimension (CD), repeatability, pattern distortion, etch performance and readiness for high volume manufacturing. With respect to CD, the investigation included absolute value change (shrinkage or growth) and CD uniformity (CDU). For pattern distortion, we investigated line shrinkage, corner rounding, and line end pull back. Defectivity checks were conducted for full wafer comparison pre and post the UV cure process. Manufacturability measures include throughput, cost of ownership and process stability.

Controlling 2D aspect ratio of elliptical contact level interconnects utilizing spin-on and reactive ion etch critical dimension shrink for the 22-nm node

Litho-Etch-Litho-Etch double patterning requires aggressive shrink of each sub-patterns critical dimensions to enable inter-digitation and pitch doubling. Application of this double patterning technique to elliptical contacts introduces a new constraint to the CD shrink processes as controlling the 2-D aspect ratio of elliptical contacts is critical for both device performance and yield. The impact of a track-applied chemical shrink and reactive ion etch [RIE] shrink processes to pre/post RIE 2-D aspect ratios [2-D AR] have been evaluated. A methodology for controlling 2-D aspect ratios with an aggressive CD shrink target is described using a 2:1 aspect ratio test pattern resulting in the successful fabrication of 2:1 aspect ratio bottom CD contacts with 65% bias from the lithographic CD.