David A. Comisky

Hub interface unit and application unit interfaces for expanded direct memory access processor

Superscalar memory transfer controller in multilevel memory organization

System and method to mitigate pots ringing interference in DSL

Request queue manager in transfer controller with hub and ports

Unified memory system architecture including cache and directly addressable static random access memory

Effective channel priority processing for transfer controller with hub and ports

Method and apparatus for operating one or more caches in conjunction with direct memory access controller

Programmer initiated cache block operations

Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access

Cache memory controlled by system address properties