Iain Robertson

Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems

Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by high speed, large scale implementation of SerDes I/Os (serial/deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper, we present the test challenges and describe on-chip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets

Novel architecture for a high performance full custom graphics processor

The design and architectural features of a 32-b microprogrammed graphics processor are discussed. A description is given of the application of datapath elements and the exploitation of VRAM hardware, to achieve state-of-the-art processor performance levels. The host interface is discussed, along with video control, screen refresh control, and emulation and testability.<<ETX>>