David Blaauw

A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes

Accurate measurement of synchronization cycle time is required for ultra-low power wireless sensor nodes with stringent power budgets. A multi-stage gate-leakage-based timer with boosted charging is proposed to address the high jitter of prior-art gate-leakage-based timers. The key approaches are faster load capacitor charging, wider voltage swing, and an improved gain sensing inverter. The proposed timer reduces RMS jitter by 8.1× and synchronization uncertainty by 4.1×, which allows hourly tracking with 200 ms uncertainty while consuming 660 pW. A novel closed-loop temperature compensation scheme with dynamic leakage adjustment is also proposed to achieve temperature sensitivity of 31 ppm/°C.

Runtime leakage minimization through probability-aware dual-V/sub t/ or dual-T/sub ox/ assignment

With process scaling runtime leakage current, when the circuit is operating, has become a major concern in addition to traditional standby mode leakage. In this paper we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either a high or a low value. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-K, (thick-oxide) that have a high likelihood of being off (on) and hence contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored for the proposed approach, where V/sub t/ and T/sub ox/ assignment with favorably trade-offs under skewed input probabilities are provided. The optimization algorithm performs simultaneous sizing, V/sub t/ and T/sub ox/ assignment and shows substantial leakage improvement over probability-unaware optimization.