David C. Uliana

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA

Many varied domain experts use Lab VIEW as a graphical system design tool to implement DSP algorithms on myriad target architectures. In this paper, we introduce the latest LabVIEW FPGA compiler that enables domain experts with minimum hardware knowledge to quickly implement, deploy, and verify their domain-specific applications on FPGA hardware. We present two compiler techniques that we use to 1) extract extra parallelism from a users application to take advantage of the parallel hardware resources of the FPGA and 2) minimize memory-access traffic, which is often a bottleneck that restricts overall FPGA performance. Finally, our approach provides the user a simple constraint-driven experience to maximize their development efficiency. We use two case studies in two different domains, a 3GPP Turbo decoder and a Smith-Waterman algorithm, to show the benefits our tool provides to users.

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture. While providing an algorithmic method to enhance parallel processing within the decoder in the first approach, in the second approach we apply the decoder architecture to achieve another highly-parallel architecture. We have successfully validated the second approach to get a 2.48Gb/s QC-LDPC decoder implementation operating at 200MHz on the Xilinx Kintex-7 FPGA in the NI USRP-2953R. For rapid-prototyping our research findings, the high-level description of the entire decoder was translated to a Hardware Description Language (HDL), namely VHDL, using the algorithmic compiler in the National Instruments LabVIEW™ Communication System Design Suite (CSDS™). As per our knowledge, at the time of writing this paper, this is the fastest FPGA-based implementation of a standard compliant QC-LDPC decoder on a USRP using an algorithmic compiler.

FPGA-based accelerator development for non-engineers

In todays world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information has become a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development flows targeting such hardware require digital design expertise. This work proposes a usable, end-to-end accelerator development methodology that attempts to bridge this gap between domain-experts and the vast computational capacity of FPGA-based heterogeneous platforms. To accomplish this, a development flow was assembled, targeting the Convey Hybrid-Core HC-1 heterogeneous platform and utilizing an existing graphical design environment for design entry. The efficacy of the flow in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at an NSF-funded summer workshop, organized and hosted by a bioinformatics organization at a particular university. A group of five life-science-focused, non-engineer participants made significant modifications to a bare-bones Smith-Waterman accelerator, extending its functionality and improving performance.