David Chau

Nusselt Number and Friction Factor of Staggered Arrays of Low Aspect Ratio Micropin-Fins Under Cross Flow for Water as Fluid

Experimental results of the thermal and hydraulic performances of silicon-based, low aspect ratio micropin-fin cold plates under cross flow conditions are reported. The pins were both circular and square in shape with dimensions (diameter for circular and sides for square) ranging from 50 μm to 150 μm. The test chip contained 20 integral 75 X 75 μm temperature sensors which were used to determine the thermal resistance (K W -1 ) of the cold plates. The experiments were conducted using water, over a Reynolds number (Re) ranging from 40 to 1000. The data show that the average Nusselt number (Nu) based on the fin diameter varies as Re 0.84 for Re 100, where Re is the Reynolds number based on maximum velocity and the fin diameter. Analysis of the Fanning friction factor (f) data shows that f varies as Re -1.35 for Re 100.

High-density compliant die-package interconnects

Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package substrate; and (2) the die-to-package interconnection, i.e. the bump, transmits the CTE-induced mismatch stresses directly to the ILD (Chandran et al., 2004). Compliant die-package interconnects (Zhu et al., 2004) substituted for conventional C4 flip-chip interconnections promises to offer reduction in package induced stresses onto the silicon die consisting of low-k ILD layers. The reduction of stresses achieved with these compliant interconnects is by decoupling the die and the package substrate such that either entity is able to deform without constraining the other. Extensive thermomechanical simulation using various modeling approaches predicts an ILD stress reduction offered by compliant interconnects to be between 17-57% relative to conventional C4 flip-chip bump. A prototype compliant interconnect structure was fabricated on a low-k ILD silicon test-chip with 180mum C4 pitch and packaged onto an organic substrate with Pb-free solder. Assembly end-of-line (EOL) data was collected to assess the ILD stress reduction, warpage analysis, Imax and electromigration performance of the compliant interconnects. The focus of this paper is a comparison of the performance of compliant die-package interconnects as a substitute for conventional C4 flip-chip bump technologies in low-k ILD architectures

Nusselt Number and Friction Factor of Staggered Arrays of Low Aspect Ratio Micro-Pin-Fins Under Cross Flow for Water as Fluid

Experimental results of the thermal and hydraulic performances of silicon-based, low aspect ratio micro-pin-fin cold plates under cross flow conditions are reported. The pins were both circular and square in shape with dimensions (diameter for circular and sides for square) ranging from 50 to 150 μm. The test chip contained 20 integral 75×75 μm temperature sensors which were used to determine the thermal resistance (K W-1 ) of the cold plates. The experiments were conducted using water, over a Reynolds number (Re) ranging from 40 to 1000. The data show that the average Nusselt number (Nu) based on the fin diameter varies as Re0.84 for Re 100, where Re is the Reynolds number based on maximum velocity and the fin diameter. Analysis of the Fanning friction factor (f) data shows that f varies as Re-1.35 for Re 100.Copyright

Feasibility study of using solid state refrigeration technologies for electronic cooling

Solid state refrigeration technologies claim no moving parts and could possibly be one of the promising technologies for electronic cooling in the future. This paper focuses on the use of a thin film thermoelectric cooler (TFTEC) directly above the hotspot to provide localized cooling. We discuss different packaging concepts including placing the TFTEC within the silicon die, between the silicon die and the copper integral heat spreader (IHS), and embedded in the IHS. Estimates of the cooling performance of each concept are provided. In addition, we discuss the modeling approaches including the required TFTEC performance parameters, heat flux through the cold side of the TFTEC device and the temperature difference of the extreme outside surface of the TFTEC device, that impact the targeted hotspot cooling. We also report the requirement curves of those two parameters in order to provide the targeted hotspot temperature reduction. Modeling results show that the performance requirements depend significantly on TFTEC efficiency which would also be discussed in this paper

Convective Performance of Package Based Single Phase Microchannel Heat Exchanger

Liquid cooling using integrated microscale heat exchangers are a promising future technology to address issues associated with integrated circuit thermal management. This paper reports the first results of microchannel heat exchangers fabricated directly in the back of silicon chips with integrated front side heaters and temperature sensors. These chips were mounted on organic substrates using C4 bumps and underfill and then these packages were mounted onto a motherboard using μPGA (Micro-Pin Grid Array) socket. The chips contained two metallic heaters; a 10 mm × 13 mm heater in order to provide uniform heating and a small 400 μm × 400 μm heater in order to simulate hotspots on actual microprocessors. The chips had multiple metallic temperature sensors distributed over the die area. Three different designs covering different widths and depths of microchannels were fabricated. The smallest width was 61 μm and the smallest depth was 180 μm. Thermal resistances and pressure drops of the three designs were measured. The best thermal resistance (junction to outlet of fluid) of 0.09 °C-cm2 /W, was obtained using a 61 μm wide and 272 μm deep microchannel. The chips were also tested under non-uniform heating conditions by powering the hotspot heaters up to a heat flux of 1250 W/cm2 . This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Experimental method of measuring C4 die bump temperature for electronics packaging

Recent trends in the semiconductor industry are driving a continuous increase in power dissipation, but require a lighter, more compact and thinner packaging technology. One of the concern areas is the increasing temperature of the C4 die bump. As the power continues to increase, the electrical current through the C4 die bump increases accordingly, resulting in increased bump temperature due to Joule self-heating and trace heating. This increased electrical current and temperature causes electro-migration failure of the C4 die bumps. In order to fully understand and avoid this failure phenomenon, we need to know the C4 die bump temperature. This has necessitated the development of a measurement method for the C4 die bump temperature. This paper discusses the methodology of measuring the C4 die bump temperature as well as results of our measurements. The experimental study includes variation of the bump current, the die power dissipation, and different enabling thermal solutions including natural convection and forced convection conditions. The experimental results show the effect of the Joule self-heating of the bump, the effect of the trace heating to the bump, the effect of the die heating and the effect of the bump and trace resistivity.

Thin film thermoelectric cooler thermal validation and product thermal performance estimation

The shrinking transistor feature sizes have resulted broadly in two different packaging thermal challenges; cooling the total thermal design power of the microprocessor, and thermal suppression of the hot spots which have progressively higher heat fluxes through silicon generations. Solid-state thin film thermoelectric coolers offer a possible solution strategy to the hot spot problems by mitigating the thermal non-uniformity of the silicon. However, considerable challenges are present in incorporating the thermoelectric coolers into a test device and thermal characterization of the prototypes. The present work captures the experimental and thermal modeling methodology that was used to characterize the thermal-electrical behavior of the prototypes. This characterization was followed up with a validation of the prototype over a range of uniform and hot spot heating. A temperature variation of less than 1degC in Tj between the experimental and modeling results were seen. In addition, less than 3% variation in electrical current supplied to the TFTEC module was seen between the experimental and modeling results. Based on the validated thermal model, a product use-condition modeling methodology was established in which the non-uniform heating of the product in use-condition was considered. This methodology was demonstrated using a product example and the hot spot temperature suppression was estimated to be 6degC, compared to the case when no thermoelectric cooler was used. Several interesting phenomena such as creation of new hot spots around the TFTEC module region were also observed

Effect of Localized Hotspot on the Thermal Performance of Two-Phase Microchannel Heat Exchanger

Microchannel heat exchangers using two-phase convective boiling is one of the most promising future technologies for the cooling of microprocessors. Heat generation on microprocessors is highly non-uniform due to the presence of multiple time-varying localized hotspots. Previous literature has primarily been focused on the performance of microchannels under uniform heating conditions. In this paper we report the performance of microchannel heat exchanger under both uniform and hotspot (non-uniform) heating conditions. We performed these experiments using a novel test setup where the test chip has multiple temperature sensors, one heater to provide uniform heating and a hotspot heater of size 400 μm × 400 μm. We report some of the preliminary results on the thermal performance of the heat exchanger. Results show that fluctuation in the wall temperature is different under hotspot heating conditions as compared to the uniform heating conditions. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

MICROCHANNEL EXPERIMENTAL STRUCTURE FOR MEASURING TEMPERATURE FIELDS DURING CONVECTIVE BOILING

This work designs and fabricates a microchannel structure for measurement of wall temperature fields in two-phase flow. The microchannel with hydraulic diameter of 100 micrometers is etched into a suspended beam of silicon with three independently heated regions and integrated doped silicon resistors sensitive to channel temperature. Doped silicon resistors are also sensitive to strain in the silicon caused by pressure transients in the channel, so sensors are designed with two different orientations and thus two different piezoresistive coefficients to allow decoupling of pressure and temperature effects. Use of a 400 micrometer wide suspended beam reduces side-wall conduction compared to a bulk sample and provides better opportunities to measure the influence of flow regimes on heat transfer coefficients in future work. Use of the central heater reduces fluid preheating in the inlet plenum. The measured temperature distributions at flowrates up to 0.25 ml/min with heat fluxes into the silicon beam up to 78 W/cm 2 show initial capabilities of the structure.

Experimental and Numberical Method of Measuring Flip Chip Die Bump Temperature for Electroncis Packing

Recent trends in the semiconductor industry are driving a continuous increase in current draw, but require a lighter, more compact and thinner packaging technology. As the electrical current through the controlled-collapse-chip-connection flip chip die bump increases, it results in increased bump and trace temperatures due to the Joule heating. Increasing electrical current and temperature have compounding effects on the electro-migration failure of the flip chip die bumps. This has necessitated the development of a measurement method to quantify the flip chip die bump temperature. This paper discusses the methodology of numerically predicting the flip chip die bump temperature. A numerical scheme is introduced which utilizes a multi-scale technique consisting of both a global model (in millimeters) and a local model (in microns). The local model, which is a subset of the global model, consists of a section of the die metal layers, flip chip bumps, and the multiple package layers. It utilizes temperature boundary conditions generated from the global model to ensure self-consistency in the approach. The local model is then used to determine the hottest temperature in the studied bumps. The current carrying capability of the bump can then be determined by the temperature value predicted