Je-Young Chang

Nusselt Number and Friction Factor of Staggered Arrays of Low Aspect Ratio Micropin-Fins Under Cross Flow for Water as Fluid

Experimental results of the thermal and hydraulic performances of silicon-based, low aspect ratio micropin-fin cold plates under cross flow conditions are reported. The pins were both circular and square in shape with dimensions (diameter for circular and sides for square) ranging from 50 μm to 150 μm. The test chip contained 20 integral 75 X 75 μm temperature sensors which were used to determine the thermal resistance (K W -1 ) of the cold plates. The experiments were conducted using water, over a Reynolds number (Re) ranging from 40 to 1000. The data show that the average Nusselt number (Nu) based on the fin diameter varies as Re 0.84 for Re 100, where Re is the Reynolds number based on maximum velocity and the fin diameter. Analysis of the Fanning friction factor (f) data shows that f varies as Re -1.35 for Re 100.

THERMAL PERFORMANCE AND KEY CHALLENGES FOR FUTURE CPU COOLING TECHNOLOGIES

Over the past few years, thermal design for cooling microprocessors has become increasingly challenging mainly because of an increase in both average power density and local power density, commonly referred to as “hot spots”. The current air cooling technologies present diminishing returns, thus it is strategically important for the microelectronics industry to establish the research and development focus for future non air-cooling technologies. This paper presents the thermal performance capability for enabling and package based cooling technologies using a range of “reasonable” boundary conditions. In the enabling area a few key main building blocks are considered: air cooling, high conductivity materials, liquid cooling (single and two-phase), thermoelectric modules integrated with heat pipes/vapor chambers, refrigeration based devices and the thermal interface materials performance. For package based technologies we present only the microchannel building block (cold plate in contact with the back-side of the die). It will be shown that as the hot spot density factor increases, package based cooling technologies should be considered for more significant cooling improvements. In addition to thermal performance, a summary of the key technical challenges are presented in the paper. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Evaporative Thermal Performance of Vapor Chambers Under Nonuniform Heating Conditions

This paper reports the test results of vapor chambers using copper post heaters and silicon die heaters. Experiments were conducted to understand the effects of nonuniform heating conditions (hot spots) on the evaporative thermal performance of vapor chambers. In contrast to the copper post heater, which provides ideal heating, a silicon chip package was developed to replicate more realistic heat source boundary conditions of microprocessors. The vapor chambers were tested for hot spot heat fluxes as high as 746 W/cm 2 . The experimental results show that evaporator thermal resistance is not sensitive to nonuniform heat conditions, i.e., it is the same as in the uniform heating case. In addition, a model was developed to predict the effective thickness of a sintered-wick layer saturated with water at the evaporator. The model assumes that the pore sizes in the sintered particle wick layer are distributed nonuniformly. With an increase of heat flux, liquid in the larger size pores are dried out first, followed by drying of smaller size pores. Statistical analysis of the pore size distribution is used to calculate the fraction of the pores that remain saturated with liquid at a given heat flux condition. The model successfully predicts the experimental results of evaporative thermal resistance of vapor chambers for both uniform and nonuniform heat fluxes.

Nusselt Number and Friction Factor of Staggered Arrays of Low Aspect Ratio Micro-Pin-Fins Under Cross Flow for Water as Fluid

Experimental results of the thermal and hydraulic performances of silicon-based, low aspect ratio micro-pin-fin cold plates under cross flow conditions are reported. The pins were both circular and square in shape with dimensions (diameter for circular and sides for square) ranging from 50 to 150 μm. The test chip contained 20 integral 75×75 μm temperature sensors which were used to determine the thermal resistance (K W-1 ) of the cold plates. The experiments were conducted using water, over a Reynolds number (Re) ranging from 40 to 1000. The data show that the average Nusselt number (Nu) based on the fin diameter varies as Re0.84 for Re 100, where Re is the Reynolds number based on maximum velocity and the fin diameter. Analysis of the Fanning friction factor (f) data shows that f varies as Re-1.35 for Re 100.Copyright

Convective Performance of Package Based Single Phase Microchannel Heat Exchanger

Liquid cooling using integrated microscale heat exchangers are a promising future technology to address issues associated with integrated circuit thermal management. This paper reports the first results of microchannel heat exchangers fabricated directly in the back of silicon chips with integrated front side heaters and temperature sensors. These chips were mounted on organic substrates using C4 bumps and underfill and then these packages were mounted onto a motherboard using μPGA (Micro-Pin Grid Array) socket. The chips contained two metallic heaters; a 10 mm × 13 mm heater in order to provide uniform heating and a small 400 μm × 400 μm heater in order to simulate hotspots on actual microprocessors. The chips had multiple metallic temperature sensors distributed over the die area. Three different designs covering different widths and depths of microchannels were fabricated. The smallest width was 61 μm and the smallest depth was 180 μm. Thermal resistances and pressure drops of the three designs were measured. The best thermal resistance (junction to outlet of fluid) of 0.09 °C-cm2 /W, was obtained using a 61 μm wide and 272 μm deep microchannel. The chips were also tested under non-uniform heating conditions by powering the hotspot heaters up to a heat flux of 1250 W/cm2 . This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Cooling of Electronic Chips Using Microchannel and Micro-Pin Fin Heat Exchangers

The research community is experiencing a revolution in microscale and nanoscale heat transfer, with a focus on developing fundamental experiments and theoretical techniques. More recently, these advancements have begun to influence the design of electronic systems. A futuristic electronic cooling solution might include high efficiency thermoelectric devices made from nanomaterials for the cooling of hotspots on a chip, nano/micro particle laden thermal interface materials and micro-pin fin/microchannel based heat exchanger. Liquid cooling using integrated microscale heat exchangers is a promising future technology to address issues associated with integrated circuit thermal management. In this paper recent advances made by us on technology development of microchannel/micro-pin-fin heat exchangers is presented. Particular attention is given to the impact of hotspots on the performance of microchannel cooling.© 2008 ASME

Effect of Localized Hotspot on the Thermal Performance of Two-Phase Microchannel Heat Exchanger

Microchannel heat exchangers using two-phase convective boiling is one of the most promising future technologies for the cooling of microprocessors. Heat generation on microprocessors is highly non-uniform due to the presence of multiple time-varying localized hotspots. Previous literature has primarily been focused on the performance of microchannels under uniform heating conditions. In this paper we report the performance of microchannel heat exchanger under both uniform and hotspot (non-uniform) heating conditions. We performed these experiments using a novel test setup where the test chip has multiple temperature sensors, one heater to provide uniform heating and a hotspot heater of size 400 μm × 400 μm. We report some of the preliminary results on the thermal performance of the heat exchanger. Results show that fluctuation in the wall temperature is different under hotspot heating conditions as compared to the uniform heating conditions. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Micro-thermal-fluid transient analysis and active control for two-phase microelectronics cooling

Because of increasing power densities, microchannel systems are being explored for two-phase cooling of ultra high power electronic devices. Flow instability is a potential problem in any two-phase microchannel cooling system especially for transient applications. With various two-phase flow stabilities possible in a microscale boiling system, the overall cooling performance deteriorates significantly. For better dynamic thermal management of microelectronic systems, a family of oscillatory flow boiling heat transfer correlations and active stabilizing flow control methods have been developed.

Thermal management of packages with 3D die stacking

The objective of thermal design requirement for 3D stacked die package is to maintain the junction temperatures of active devices in the package at or below specified limits. In this paper, die-to-die thermal resistance is identified as the key bottleneck in 3D thermal management, and two solution paths are proposed: fully-populated thermal bump array and thermally conductive underfill materials. The sensitivity of the thermal bump array design and the effective thermal conductivity of underfill materials will be discussed. In addition to die-to-die thermal resistance reduction, enhancement of the overall packaging cooling capability by integrating liquid cooling to the package heat spreader is another option especially for the server type of environment which typically dissipates high power. An alternative approach is to integrate thermo-electric cooling to the heat spreader for hot spot cooling. For systems that are limited to traditional air cooling, this paper will propose a different package architecture which will utilize existing cooling capability of 3D die stacking. Although the power dissipation capability of 3D die stacking is worse than the 2D multiple-chip packages, dual-die stacking can potentially achieve a higher efficiency of “performance per power” by utilizing the same concept of dual-core microprocessor. This approach is very useful especially when the package real estate is limited and 3D die stacking is the preferred package architecture.

Compact Thermal Modeling Methodology for Active and Thermal Bumps in 3D Microelectronic Packages

Accurate estimation of the thermal conductivity of logic-memory and memory-memory interfaces, between stacked die in 3D microelectronic packages, is key to effective design and early estimates of performance and reliability. Typically, interconnect layers contain hundreds to a few thousands of bumps. Hence lumped/compact modeling of this interfacial layer is essential to reduce computational time and complexity. The typical approach to this lumped modeling is to estimate the effective conductivity of the layer by assuming the bumps and underfill regions can be modelled as parallel thermal resistances (referred to as the volumetric method). This work demonstrates that the volumetric method can significantly underpredict 3D stack thermal resistance and junction temperatures. An alternative method-referred to as the single bump method-of estimation of the thermal conductivity of interconnect layers in 3D stacked-die packages is presented. Studies demonstrate that the proposed single bump method captures the heat transfer in these interfaces accurately. Validation of the single bump modeling is presented by comparing the single bump and volumetric methods with fully discretized models. This comparison also demonstrates that the prevalent volumetric method overestimates the effective thermal conductivity of the interface, while the single bump approach results in more accurate assessment of 3D stack resistance.Copyright