David H. Robertson

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR

A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-/spl mu/m CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal.

A wideband 10-bit, 20 Msps pipelined ADC using current-mode signals

A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures. Although multistage ADCs are efficient in both die area and power, a track-and-hold amplifier (T/H) is required to prevent the input from changing while a conversion is taking place. If the ADC is pipelined (operating on more than one sample at a time), a T/H is required between each pipeline stage. Additionally, for resolution greater than about 8 b interstage amplification is required. The settling behavior of the T/Hs and amplifiers dominates the performance of these ADCs. To address these problems, a differential current-mode architecture incorporates current-mode T/Hs, obviating the need for interstage amplifiers. The prototype chip achieves 10 b of resolution at 20 Msample/s with an 80-MHz input bandwidth and dissipates 1 W.<<ETX>>

A 16b /spl Sigma//spl Delta/ pipeline ADC with 2.5 MHz output data-rate

A 16b 2.5 MHz A/D converter in 0.6 /spl mu/m CMOS addresses the need for wide dynamic range A/D converters with bandwidths in excess of 1 MHz in multi-tone communication. This A/D converter combines the advantages of /spl Sigma//spl Delta/ and pipeline A/D conversion techniques to provide wide dynamic range at a low-oversampling ratio. The device operates at a 20 MHz clock rate, 2.5 MHz output rate (8/spl times/ oversampling), and provides 89 dB SNR over a 1.25 MHz input bandwidth.

Cascaded sigma-delta pipelien A/D converter with 1.25 MHz signal bandwidth and 89 DB SNR

A low-noise multibit sigma–delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6m CMOS process, cascades a second-order 5-b sigma–delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of 98 dB with a 100-kHz input signal.

F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX

Data converters continue to push the boundaries of performance by achieving higher sampling speeds and wider bandwidths. In todays data converters, GS/s is starting to become common-place. This forum brings together experts from industry and academia to talk about recent advancements that have enabled these breakthroughs. These experts will present the state-of-the-art and address design challenges pertaining to a wide range of topics (GS/s pipes & multi-GHz sampling in DS Modulators, high-speed SAR ADCs, high-speed DACs, hybrid data converters and time-domain converters). The forum will conclude with a panel discussion with the speakers.

Data converter reflections: 19 papers from the last ten years that deserve a second look

The authors discuss several papers that have been presented over the last decade that are worth additional consideration by readers interested in data converter circuits. The papers have been selected for different reasons: some have become trend-setters, others present particularly interesting ideas that may yet set future trends.

BiCMOS techniques for high speed, high resolution A/D converters

The author discusses the advantages of BiCMOS technology in the implementation of high-speed, high-resolution analog/digital converters. Consideration is given to how high-speed analog requirements affect device and topology selection. Several illustrative examples are provided to illustrate how BiCMOS can provide a performance advantage over the straight CMOS implementations and a flexibility/functionality advantage over the pure bipolar topologies.<<ETX>>