Christopher W. Mangelsdorf

A 400-MHz input flash converter with error correction

An 8-b, 200-megasample/s flash converter with 400-MHz analog bandwidth and error correction circuitry is described. A cascoded input stage and a dense bipolar process make the wide bandwidth possible. Errors arising from high input slew rate and comparator metastability are reduced by means of the circuitry and the latching stages respectively. The final defense against errors is the second rank error suppression. Measured frequency and error rate performance are examined. >

A variable gain CMOS amplifier with exponential gain control

A variable gain amplifier architecture suitable for foundry CMOS is constructed using linearized transconductance blocks. The use of a four-transistor transconductance cell allows for wider gain range and larger signal swing under low supply conditions than the simple differential pair used in previous work. Experimental results with 0.6 /spl mu/m CMOS show -5 to 35 dB gain and 20 MHz bandwidth at 21 mW.

A wideband 10-bit, 20 Msps pipelined ADC using current-mode signals

A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures. Although multistage ADCs are efficient in both die area and power, a track-and-hold amplifier (T/H) is required to prevent the input from changing while a conversion is taking place. If the ADC is pipelined (operating on more than one sample at a time), a T/H is required between each pipeline stage. Additionally, for resolution greater than about 8 b interstage amplification is required. The settling behavior of the T/Hs and amplifiers dominates the performance of these ADCs. To address these problems, a differential current-mode architecture incorporates current-mode T/Hs, obviating the need for interstage amplifiers. The prototype chip achieves 10 b of resolution at 20 Msample/s with an 80-MHz input bandwidth and dissipates 1 W.<<ETX>>

A CMOS front-end for CCD cameras

Most modern camcorders use digital processing exclusively in the signal path for better performance even though image information from the CCD and the signal recorded on the internal VTR are both in analog form. Before the signal can be digitized, however, extensive clamping and low-noise gain must be applied. Consumer pressure for small camcorder size and low power have lead to the development of a system in which all the functions previously residing on a bipolar chip have been incorporated on the same CMOS die with the ADC, including a CDS block, an amplifier with variable gain from 0 to 34 dB, a black-level correction loop, an input clamp and a voltage reference. An emitter follower buffer is traditionally used between the CCD and the rest of the system for line driving, but this is the only portion of the analog signal chain external to the chip.

A two-residue architecture for multistage ADCs

An architecture for multistage ADCs (analog-to-digital converters) that uses two residue signals to reduce amplifier requirements is described. The residue at any stage in a multistage ADC is the difference between the analog signal and the closest quantization level. A second residue is defined here as the difference between the analog signal and the second closest quantization level. The job of the subsequent stages is to decide where the analog signal lies between these two quantization levels. By passing both residues to subsequent stages, information is propagated about the exact size of the quantization step, because the sum of the two residues is equal to the difference between the two quantization levels (or an LSB of the quantizer). Conceptually, the two residues carry their own reference. The complete 10-b, three-stage pipeline ADC is shown.<<ETX>>

Design for testability in digitally-corrected ADCs

A test methodology that reveals safety-margin problems is presented. The methodology allows diagnosis without additional hardware. To test the safety margin, the correction logic is inhibited. The coding of the first and second stages actually remains the same, but the first stage output is never decremented before the two stage outputs are combined to form the overall ADC (analog-to-digital converter) output code. This means that over a portion of the second-stage range, the ADC output code will be too high. An example of how a first-stage flash error is interpreted is shown. Here the safety margin is reduced by the shift of the first-stage transition. The technique described here has been demonstrated on a CMOS 10-b, 20-Ms/s ADC for camcorder applications.<<ETX>>

A Little In Front O' The Next

For many people, the first experience of Paul Brokaw is a job interview. Unfortunately, for many people, it is also their last. It?s not that Paul makes the interview uncomfortable. On the contrary, it is relaxed and friendly. It feels more like the meeting of old colleagues than a formal interview. It is quickly apparent, however, that this is going to be something different, and whatever you trained for, whatever you think you know, it?s not going to be enough.

The future role of the analog designer

A summary on the future role of the analog designer is presented. It is pointed out that the role of the analog designer will be to create high-performance circuits that enhance the entire system, and that analog design is being expanded to include mixed-analog-digital design.<<ETX>>