David Howard

A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design

We present a broad-band lumped element planar inductor model that is suitable for RFIC design in silicon technologies. We provide extensions of the modeling methodology to similar components such as differential inductors, baluns, and solenoid inductors. The analytic computation of the physics-based model components, incorporating both metal skin effect and substrate loss, is described. The model is validated using measured data from over 200 inductors made with five different silicon back-end process technologies. The physics-based implementation of the model allows its use for determining the optimum process technology characteristics for specific radio frequency integrated circuit (RFIC) designs. The analytical based implementation with lumped elements enables effective integration into a robust CAD system for efficient design of RFIC circuits.

Recent developments using TowerJazz SiGe BiCMOS platform for mmWave and THz applications

In this paper, we report on the highest speed 240GHz/340GHz FT/FMAX NPN which is now available for product designs in the SBC18H4 process variant of TowerJazz’s mature 0.18μm SBC18 silicon germanium (SiGe) BiCMOS technology platform. NFMIN of ~2dB at 50GHz has been obtained with these NPNs. We also describe the integration of earlier generation NPNs with FT/FMAX of 240GHz/280GHz into SBC13H3, a 0.13μm SiGe BiCMOS technology platform. Next, we detail the integration of the deep silicon via (DSV), through silicon via (TSV), high-resistivity substrate, sub-field stitching and hybrid-stitching capability into the 0.18μm SBC18 technology platform to enable higher performance and highly integrated product designs. The integration of SBC18H3 into a thick-film SOI substrate, with essentially unchanged FT and FMAX, is also described. We also report on recent circuit demonstrations using the SBC18H3 platform: (1) a 4-element phased-array 70-100GHz broadband transmit and receive chip with flat saturated power greater than 5dBm and conversion gain of 33dB; (2) a fully integrated W-band 9-element phase-controllable array with responsivity of 800MV/W and receiver NETD is 0.45K with 20ms integration time; (3) a 16-element 4x4 phased-array transmitter with scanning in both the E- and H-planes with maximum EIRP of 23-25 dBm at 100-110GHz; (4) a power efficient 200GHz VCO with -7.25dBm output power and tuning range of 3.5%; and (5) a 320GHz 16-element imaging receiver array with responsivity of 18KV/W at 315GHz, a 3dB bandwidth of 25GHz and a low NEP of 34pW/Hz1/2. Wafer-scale large-die implementation of the phased-arrays and mmWave imagers using stitching in TowerJazz SBC18 process are also discussed.

Scaling and application of commercial, feature-rich, modular mixed- signal technology platforms for large format ROICs

Todays modular, mixed-signal CMOS process platforms are excellent choices for manufacturing of highly integrated, large-format read out integrated circuits (ROICs). Platform features, that can be used for both cooled and un-cooled ROIC applications, can include (1) quality passives such as 4fFμm2 stacked MIM capacitors for linearity and higher density capacitance per pixel, 1kOhm high-value poly-silicon resistors, 2.8μm thick metals for efficient power distribution and reduced I-R drop; (2) analog active devices such as low noise single gate 3.3V, and 1.8V/3.3V or 1.8V/5V dual gate configurations, 40V LDMOS FETs, and NPN and PNP devices, deep n-well for substrate isolation for analog blocks and digital logic; (3) tools to assist the circuit designer such as models for cryogenic temperatures, CAD assistance for metal density uniformity determination, statistical, X-sigma and PCM-based models for corner validation and to simulate design sensitivity, and (4) sub-field stitching for large die. The TowerJazz platform of technology for 0.50μm, 0.25μm and 0.18μm CMOS nodes, with features as described above, is described in detail in this paper.

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.