Paolo Miliozzi

Modeling digital substrate noise injection in mixed-signal IC's

Techniques are presented to compactly represent substrate noise currents injected by digital networks. Using device-level simulation, every gate in a given library is modeled by means of the signal waveform it injects into the substrate, depending on its input transition scheme. For a given sequence of input vectors, the switching activity of every node in the Boolean network is computed. Assuming that technology mapping has been performed, each node corresponds to a gate in the library, hence, to a specific injection waveform. The noise contribution of each node is computed by convolving its switching activity with the associated injection waveforms. The total injected noise for the digital block is then obtained by summing all the noise contributions in the circuit. The resulting injected noise can be viewed as a random process, whose power spectrum is computed using standard signal processing techniques. A study was performed on a number of standard benchmark circuits to verify the validity of the assumptions and to measure the accuracy of the obtained power spectra.

SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs

A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.

A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design

We present a broad-band lumped element planar inductor model that is suitable for RFIC design in silicon technologies. We provide extensions of the modeling methodology to similar components such as differential inductors, baluns, and solenoid inductors. The analytic computation of the physics-based model components, incorporating both metal skin effect and substrate loss, is described. The model is validated using measured data from over 200 inductors made with five different silicon back-end process technologies. The physics-based implementation of the model allows its use for determining the optimum process technology characteristics for specific radio frequency integrated circuit (RFIC) designs. The analytical based implementation with lumped elements enables effective integration into a robust CAD system for efficient design of RFIC circuits.

A video driver system designed using a top-down, constraint-driven methodology

To accelerate the design cycle for analog and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. The key idea of the proposed methodology is hierarchically propagating constraints from performance specifications to layout. Consequently, it is essential to provide the necessary tools and techniques enabling the efficient constraint propagation. To illustrate the applicability of the proposed methodology to the design of larger systems, we present in this paper the complete design flow for a video driver system. Critical advantages of the methodology illustrated with this design example include avoiding costly low level re-designs and getting working silicon parts from the first run. Following our approach, a jitter constraint is imposed at the system level and then is propagated hierarchically to the circuit blocks and layout, using behavioral modeling and simulation. Experimental results are presented from working fabricated parts.

A design system for RFIC: challenges and solutions

The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having a good design methodology, innovation computer-aided design (CAD) tools, and a well-integrated design system are key factors for success. In this paper, we describe a design system developed to provide the designer with everything necessary to accurately predict the behavior of RFIC devices, including layout and package parasitic effects. We show how important a well-defined and integrated system is to manufacturing a design that meets specifications at the minimum cost, in the minimum time. A close link between schematic, models, and layout is of paramount importance to ensure the accuracy need for low-power RF design. We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success.

Modeling of substrate noise injected by digital libraries

Switching noise is one of the major sources of timing errors and functional hazards in logic circuits. It is caused by the cumulative effect of microscopic spurious currents arising in all devices during logic transitions. These currents are injected into the substrate and in supply lines, resulting in significant ripple noise. Individually, such micro-currents do not usually cause catastrophic failures. However, cumulatively, they can impact power supply and substrate potential across the chip. Thus, the electrical behavior of sensitive digital and analog circuits can be significantly changed, hence limiting circuit performance. The analysis of switching noise at a macroscopic level requires one to accurately compute models for all microscopic spurious currents, known as noise signatures. The challenge is to simultaneously account for a myriad of parameters and their process variations in a compact and accurate model. To address this problem, a new methodology based on response surface methodology and orthogonal polynomial approximation is proposed. Experimental results on a 0.35 /spl mu/m library show that the methodology is capable of accurately approximating noise signatures with a single analytical formula. A library of such formulae has been created and it is being used to accurately characterize switching noise at the macroscopic level.

Use of sensitivities and generalized substrate models in mixed-signal IC design

A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal. Circuits in presence of layout parasitics and substrate induced noise. Accurate and efficient evaluation of the circuit during design is possible by taking into account such non-idealities. Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the layout. Verification is performed using substrate extraction in combination with parasitic estimation techniques. To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1 /spl mu/m technology. The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.

Generalized constraint generation in the presence of non-deterministic parasitics

In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements, of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design.

High-level design case of a switched-capacitor low-pass filter using Verilog-A

System design requires experienced designers that use heuristics and built up knowledge to propose a high order solution. Behavioral models can help to formalise, optimise and speed up this design cycle. A design case is presented that shows how behavioral models are used to support system design. Models of two basic analog functions (operational amplifier and switch) are developed in Verilog-A and used in the design of a 1/sup st/-order switched-capacitor low-pass filter. This allows one to find a first-order system solution on a higher level than the fully designed transistor schematic. The specifications of the subblocks can then be refined rapidly into a transistor netlist by an analog designer.

A benchmark suite for substrate analysis

The paper proposes an initial benchmark set, suitable for substrate analysis and test. The aim is to help accurately represent electrical noise injected into and picked up from substrate in a variety of high performance circuits. Creating an accurate image of such noise is becoming a critical requirement with the expansion of real plug-and-play style designs. Several important methods for the analysis of substrate parasitic coupling are reviewed in light of the effect substrate noise has on the performance of analog and digital ICs over a wide frequency spectrum. The requirements and formats for each benchmark are described in full detail to allow possible algorithmic as well as signal integrity tests.