David Kearney

Bundled data asynchronous multipliers with data dependent computation times

A novel asynchronous design method is introduced which combines the area efficiency of bundled data with data dependent computation time. The design of a 16/spl times/16 bit multiplier using this technique is explained and evaluated. Simulation results show that area time savings of 20% compared to an equivalent synchronous design can be achieved.

Performance evaluation of asynchronous logic pipelines with data dependent processing delays

Among the claims made concerning the advantages of asynchronous logic are that circuits can take advantage of average case (data dependent) speed rather than worst case speed. Whilst this argument can easily be sustained for a single logic stage its extension to systems consisting of many logic stages has not been widely investigated. This paper reports on investigations into the throughput of asynchronous and synchronous pipelines consisting of alternate latches and logic stages where the data dependent delay is a two valued random variable. The extent to which an average case speed of a single stage which is lower than worst case can be translated into higher throughput in an asynchronous pipeline as compared to a synchronous pipeline is found to be restricted by the coefficient of variation of the distribution of data dependent delay, the length of the pipeline, the number of latches used between each logic stage and the number data items in a loop.

A region-oriented hardware implementation for membrane computing applications

We have recently developed a prototype hardware implementation of membrane computing based on reconfigurable computing technology called Reconfig-P. The existing hardware design treats reaction rules as the primary computational entities and represents regions only implicitly. In this paper, we describe and evaluate an alternative hardware design that more directly reflects the intuitive conceptual understanding of a P system and therefore promotes the extensibility of Reconfig-P. A key feature of the design is the fact that regions, rather than reaction rules, are the primary computational entities. More specifically, in the design, regions are represented as loosely coupled processing units which communicate objects by message passing. Experimental results show that for many P systems the region-oriented and rule-oriented designs exhibit similar performance and hardware resource consumption.

An Algorithm for Non-deterministic Object Distribution in P Systems and Its Implementation in Hardware

We have recently developed a prototype hardware implementation of membrane computing using reconfigurable computing technology. This prototype, called Reconfig-P, exhibits a good balance of performance, flexibility and scalability. However, it does not yet implement non-deterministic object distribution. One of our goals is to incorporate non-deterministic object distribution into Reconfig-P without compromising too significantly its performance, flexibility or scalability. In this paper, we (a) propose an algorithm for non-deterministic object distribution in P systems, and (b) describe and evaluate a prototype hardware implementation of this algorithm based on reconfigurable computing technology. The results of our evaluation of the prototype implementation show that our proposed algorithm can be efficiently implemented using reconfigurable computing technology. Therefore there is strong evidence that it is feasible to incorporate non-deterministic object distribution into Reconfig-P as desired.

Fast 2D convolution using reconfigurable computing

Convolution and its related counterpart correlation are two commonly used operations in image processing. However these operations are computationally expensive, and perform sluggishly when implemented on microprocessors. Part of the poor performance is due to the serial nature of microprocessors, while the operations of convolution and correlation are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASICs). Another approach is to use Field Programmable Gate Arrays (FPGAs) and reconfigurable computing. Reconfigurable computing offers a trade-off between the flexibility of software running on a microprocessor and the speed of custom designed hardware. This paper describes a parallel pipelined architecture for 2D convolution written in Handel-C for a reconfigurable computing platform. The resulting system offered a 400 times increase in speed over software written in C.

Image fusion for uninhabited airborne vehicles

In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infrared and synthetic aperture radar imaging sensors, so image fusion is an appropriate onboard processing task for UAVs. Some forms of image fusion are computationally intensive tasks, but like many other image processing applications are naturally suited to acceleration in hardware. This potential for hardware acceleration, and the ability to reconfigure the UAV to implement new algorithms as it moves towards objects of interest make reconfigurable computing a natural route for a hardware implementation. In this paper we present what we believe is the first implementation of image fusion on a reconfigurable platform alone, and the first investigation of adaptive image fusion which makes use of dynamic reconfiguration to change the fusion algorithm as the UAV approaches an object of interest.

Theoretical limits on the data dependent performance of asynchronous circuits

Speculations about the ability of asynchronous systems to take advantage of the data dependent performance of circuit components have been widespread. Simulations and actual designs have not however provided much confirmation that it is possible to transfer the average case data dependent performance of a single stage into average case performance of a system without paying an unacceptable area penalty in the implementation. Here it is shown that if area*time is chosen as the performance metric to be minimized there are in fact absolute theoretical limits to achieving data dependent performance as compared with synchronous circuits. These limits are shown to arise in two completely different theoretical approaches each of which make few assumptions about the distribution of data dependent delays experienced when the circuit operates. The theoretical approach confirms many of the tradeoffs that designers of data dependent circuits have long suspected.

Balancing performance, flexibility, and scalability in a parallel computing platform for membrane computing applications

It is an open question whether it is feasible to develop a parallel computing platform for membrane computing applications that significantly outperforms equivalent sequential computing platforms while still achieving acceptable flexibility and scalability. To move closer to an answer to this question, we have investigated a novel approach to the development of a parallel computing platform for membrane computing applications that has the potential to deliver a good balance between performance, flexibility and scalability. This approach involves the use of reconfigurable hardware and an intelligent software component that is able to configure the hardware to suit the specific properties of the membrane computing model to be executed. We have already developed a prototype computing platform called Reconfig-P based on the approach. Reconfig-P is the first computing platform of its type to implement parallelism at both the system and region levels. In this paper, we describe the functionality of the intelligent software component responsible for hard-ware configuration in Reconfig-P, and perform an empirical analysis of the performance, flexibility and scalability of Reconfig-P. The empirical results suggest that the implementation approach on which Reconfig-P is based is a viable means of attaining a good balance between performance, flexibility and scalability.

A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm

Many computer simulations require large quantities of uncorrelated random numbers to be generated quickly. Examples include all forms of Monte Carlo simulation, generating phase screens to simulate the effects of atmospheric turbulence and the simulation of electrical noise in sensors. A flexible way to generate random numbers of arbitrary distribution is to modify the distribution of a source of uniform random numbers. Thus it is of interest to have a fast uniform random number generator implemented in reconfigurable hardware. In this paper we present multiple hardware implementations of the TT800 algorithm. The best implementation achieved a throughput of 4.6times109 uniform random numbers per second using 24 parallel generators by making use of 253 Xilinx Virtex XC2VP70 slices. It has an area time rating of 0.05times10-6 Xilinx slices x seconds per 32 bit random number. It has the lowest area time metric and only half the area requirement than the previously best published multi-port, single seed generator with at least a 2800 period.

Towards a reconfigurable tracking system

Robust real-time automatic detection tracking and classification of objects in imagery is one of the most computationally demanding tasks in computer vision. Historically the field of computer vision has been limited by computing power. In particular algorithms that require multiple correlations, convolutions and other complex operations can be prohibitive to implement on a microprocessor. Part of the poor performance of microprocessors is their serial nature, while many of these operations are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASIC). Another approach is to use Field Programmable Gate Arrays (FPGAs) and reconfigurable computing. Reconfigurable computing offers a trade-off between the speed of hardware and flexibility of software. This paper describes two computationally intensive tracking algorithms, investigates their implementation on a reconfigurable computer, and benchmarks their performance. From our preliminary results we find that reconfigurable computing is well suited to the implementation of real-time tracking systems.