Mark Jasiunas

On Implementing High Level Concurrency in Java

Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant language extension to express concurrency and synchronization. This language called Join Java has all the expressiveness of Object Oriented languages whilst offering the added benefit of superior synchronization and concurrency semantics. Join Java incorporates asynchronous method calls and message passing. Synchronisation is expressed by a conjunction of method calls that execute associated code only when all parts of the condition are satisfied. A prototype of the Join Java language extension has been implemented using a fully functional Java compiler allowing us to illustrate how the extension preserves Join semantics within the Java language. This paper reviews the issues surrounding the addition of Join calculus constructs to an Object Oriented language and our implementation with Java. We describe how, whilst the Join calculus is non-deterministic, a form of determinism can and should be specified in Join Java. We explain the need for a sophisticated yet fast pattern matcher to be present to support the Join Java compiler. We also give reasons why inheritance of Join patterns is restricted in our initial implementation.

Fast 2D convolution using reconfigurable computing

Convolution and its related counterpart correlation are two commonly used operations in image processing. However these operations are computationally expensive, and perform sluggishly when implemented on microprocessors. Part of the poor performance is due to the serial nature of microprocessors, while the operations of convolution and correlation are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASICs). Another approach is to use Field Programmable Gate Arrays (FPGAs) and reconfigurable computing. Reconfigurable computing offers a trade-off between the flexibility of software running on a microprocessor and the speed of custom designed hardware. This paper describes a parallel pipelined architecture for 2D convolution written in Handel-C for a reconfigurable computing platform. The resulting system offered a 400 times increase in speed over software written in C.

Image fusion for uninhabited airborne vehicles

In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infrared and synthetic aperture radar imaging sensors, so image fusion is an appropriate onboard processing task for UAVs. Some forms of image fusion are computationally intensive tasks, but like many other image processing applications are naturally suited to acceleration in hardware. This potential for hardware acceleration, and the ability to reconfigure the UAV to implement new algorithms as it moves towards objects of interest make reconfigurable computing a natural route for a hardware implementation. In this paper we present what we believe is the first implementation of image fusion on a reconfigurable platform alone, and the first investigation of adaptive image fusion which makes use of dynamic reconfiguration to change the fusion algorithm as the UAV approaches an object of interest.

Towards a reconfigurable tracking system

Robust real-time automatic detection tracking and classification of objects in imagery is one of the most computationally demanding tasks in computer vision. Historically the field of computer vision has been limited by computing power. In particular algorithms that require multiple correlations, convolutions and other complex operations can be prohibitive to implement on a microprocessor. Part of the poor performance of microprocessors is their serial nature, while many of these operations are inherently parallel. One approach to implementing these operations in parallel is to build them in hardware using application specific integrated circuits (ASIC). Another approach is to use Field Programmable Gate Arrays (FPGAs) and reconfigurable computing. Reconfigurable computing offers a trade-off between the speed of hardware and flexibility of software. This paper describes two computationally intensive tracking algorithms, investigates their implementation on a reconfigurable computer, and benchmarks their performance. From our preliminary results we find that reconfigurable computing is well suited to the implementation of real-time tracking systems.

ReConfigME: a detailed implementation of an operating system for reconfigurable computing

Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. In this paper, we present an implementation of an operating system that has the ability to share its FPGA resources dynamically among multiple executing applications.

A low cost, high performance reconfigurable computing based unmanned aerial vehicle

It has previously been stated that connectivity, computational processing power, and lack of resource integration are the three major limiting factors in developing the capabilities of small low-cost autonomous unmanned aerial vehicles (UAV). In an endeavor to address and overcome these limitations, we present details on a new UAV platform consisting of a commercially available airframe, off-the-shelf reconfigurable computing hardware, and a custom built operating system which does just that. This involved firstly selecting an appropriate UAV airframe which met all of the necessary specifications including cargo size and takeoff weight. Secondly, computing hardware which can provide enough computational processing power was then selected and installed into the UAV. Thirdly, the necessary software that will manage the UAV flight controls and applications was then developed and deployed. To verify the UAV platform, it was put through a series of flight trials while performing applications such as target recognition and edge detection. The significance of this research is that we have shown that complex computational applications can be performed on small, low cost UAVs

Combined run-time area allocation and long line re-routing for reconfigurable computing

On-line (run time) algorithms for allocation of area and routing resources are a requirement if field programmable logic applications are to be loaded to the FPGA at the arbitrary request of users. Long lines are the preferred interconnect for such applications on dense FPGAs as they provide low delay channels. In this paper we investigate the combination of an area allocation algorithm based on the Minkowski sum with run time routing based on line probing for applications that are linked only by long lines. We show by construction that allocation and routing are feasible at run time using these algorithms. The paper then introduces a new metric to measure the performance of dynamic run time resource allocation on FPGAs. The new metric measures fragmentation of resources in an environment where applications selected from statistical distributions of area and execution time are continuously queued for placement on the FPGA. It is argued that this metric is more realistic compared to other measures which are based on static model of allocation. A simulation of this dynamic FPGA environment has revealed new behaviours related to run time reconfiguration. Firstly, to maintain full utilisation of the area resources of the FPGA, it will be necessary to queue tasks prior to execution. The queuing time of these tasks is an added overhead not previously reported. Secondly, small area applications may block other applications due to the exhaustion of long line routing resources. This adds to the other already observed blocking behaviour where large area cores may so dominate the FPGA area that further allocation is prevented. A new operation for the aggregation of small cores is proposed in this paper to overcome blocking associated with routing.

Using simulated partial dynamic run-time reconfiguration to share embedded FPGA compute and power resources across a swarm of unpiloted airborne vehicles

We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGAs resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarmbased on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

Connectivity, Resource Integration, and High Performance Reconfigurable Computing for Autonomous UAVs

In an investigation into the capabilities of small autonomous formations of unmanned aerial vehicles (UAVs), we identified connectivity, processing power, and lack of resource integration as three major limiting factors of current technology. In an endeavor to address these issues, we propose a new novel hardware and software environment consisting of a traditional Von Neumann processor coupled with a field programmable gate array (FPGA) for high performance processing, along with support libraries to better manage the resources of a formation. The supporting software libraries have the primary functions of allowing any networked resource (such as processors and UAV sensors) to be accessed from any location in the UAV formation, and also provide support that allows algorithms implemented simultaneously on the reconfigurable and traditional processors to migrate between UAVs for better connectivity to resources or to balance processing loads. In this paper we present the issues we faced in the design of these systems, along with our preliminary results indicating the advantages and shortcomings of the system. We also describe in detail the construction of the prototype systems used to determine the correct software settings for the mobile algorithms

A multi-interface, multi-profiling system for chronic disease management learning

A key aspect of successful chronic disease management is active partnership between consumer and provider - this is particularly important in diabetes management, where many key activities are in the hands of the patient. We have developed a multi-interface system that promotes high quality diabetes management through profiling and adaptive support of both consumer and provider in the context of a university podiatry clinic. Handheld devices are used for decision support, data capture and notification of patient concerns in consultation. Consultation data integrates with Web based learning environments for podiatry students and consumers. The architecture implements our approach to patient provider partnership and exemplifies integration of system goals across platforms, users and devices. Upcoming field trials assess whether we have achieved an acceptable system that improves quality of management activities.