David Kim

Trade-off between Inverse Lithography Mask Complexity and Lithographic Performance

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.

Mask Pattern Recovery by Level Set Method based Inverse Inspection Technology (IIT) and its Application on Defect Auto Disposition

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Inverse lithography (ILT) mask manufacturability for full-chip Device

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance and need to be enabled for production as one of the leading candidates for low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (ISTM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT needs to be studied at full chip level with various aspects including mask data fracturing, MRC constraints, writing time, and inspection. The computation of ILT mask usually starts with the calculation of an optimized contoured mask then followed by manhattanization step to convert contour into horizontal-vertical segments. By varying the segmentation length during manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of segmentation length impact on writing time and lithography performance at full-chip is presented. MRC is another important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and inspectability at various selected MRC rules are also presented in the paper.

E-beam writing time improvement for Inverse Lithography Technology mask for full-chip

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[4,5], it has been shown that the Inverse Synthesizer (ISTM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.

Writing 32nm-hp contacts with curvilinear assist features

In writing contacts at 32nm half-pitch with 193nm immersion lithography, circular main features and curvilinear subresolution assist features will be desirable on masks. Using conventional methods, the best depth of focus, exposure latitude, and critical dimension uniformity on wafer could only be achieved with unrealizable mask write times. Previous papers have described a gradual improvement over the past two years to avoid this trade-off. For example, Manhattanization of the shapes generated by inverse lithography techniques has reduced the required shot count while maintaining best process windows. Using the MB-MDP technique, total shot count required to print such Manhattanized assist features is further reduced significantly. This paper is the first to present test writing results of 32nm-hp patterns using a conventional variable shaped beam mask writer with the new MB-MDP technique. Using this new technique, best process window and improved critical dimension uniformity are achieved while demonstrating reduced shot count. SEM images of resist patterns written by a production mask writer will be shown.

Best depth of focus on 22-nm logic wafers with less shot count

The contact layer for the 22 nm logic node faces many technological hurdles. Even using techniques such as multiple-exposure patterning and 193 nm immersion, it will be difficult to achieve the depth of focus and CD uniformity required for 22 nm production. Such difficulties can be mitigated by recent advances in Inverse Lithography Technology (ILT). For example, circular main features combined with complex curvilinear assist features can provide superior CD uniformity with the required depth of focus, particularly for isolated contacts. However, such a solution can lead to long mask write times, because the curvilinear shapes necessitate a higher shot count induced by inefficient data fracturing, even without considering the circular main features. The current approach is to Manhattanize the curvilinear features resulting in a nearly equivalent image quality on the wafer; but a further reduction in mask write times could help lower costs. This paper describes a novel mask-writing method that uses a production e-beam mask writer to write main features as circles, with curvilinear assist features, while reducing shot count compared to traditional Manhattanized masks. As a result the new method makes manufacturing of ideal ILT-type masks feasible from a technical as well as from an economic standpoint. Resist-exposed SEM images are presented that validate the new method.

Improving inspectability with KLA-Tencor TeraScan thin line de-sense

In the ever-changing semi-conductor industry, new innovations and technical advances constantly bring new challenges to fabs, mask-shops and vendors. One of such advances is an aggressive optical proximity correction (OPC) method, sub-resolution assist features (SRAF). On one hand, SRAFs bring a leap forward in resolution improvement during wafer printing; on the other hand they bring new challenges to many processes in mask making. KLA-Tencor Corp. working together with Samsung Electronics Co. developed an additional function to the current HiRes 1 detector to increase inspectability and usable sensitivity during the inspection step of the mask making process. SRAFs bring an unique challenge to the mask inspection process, which mask shops had not experienced before. SRAF by nature do not resolve on wafer and thus have a higher tolerance in the CD (critical dimension) uniformity, edge roughness and pattern defects. This new function, Thin-Line De-sense (TLD), increase the inspectability and usable sensitivity by generating different regions of sensitivity and thus will match the defect requirement on a particular photomask with SRAFs better. The value of TLD was proven in a production setting with more than 30 masks inspected, and resulted in higher sensitivity on main features and a sharp decrease in the amount of defects that needed to be classified.

Advanced reticle inspection challenges and solutions for 65nm node

Silicon Technology Development for the ITRS 65nm-node is in the final stage of an intense 2-year cycle with the full-entitlement technology qualification by the end of 2005. Accordingly, reticle technology development in support of the 65nm-node has advanced a great deal since the initial efforts began several years ago. One of the most challenging aspects of 65nm-node mask technology development is the mask inspection, which is also the main cost-driver for the 65nm-node reticle technology. As a result, controlling 65nm-node reticle cost via leveraging advanced mask inspection technologies has become a leading factor in enabling prolonged success of the 65-nm node technology for years to come. With this paper, we report our closing work on reticle inspection capability development for the 65nm-node process technology development cycle for a full-volume production ramp.

Affordable and Process Window Increasing Full Chip ILT Masks

To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[1,2], it has been shown that the Inverse Synthesizer (ISTM) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask. To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

Improvement of KrF contact layer by inverse lithography technology with assist feature

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.