Vikram Tolani

Trade-off between Inverse Lithography Mask Complexity and Lithographic Performance

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.

LER transfer from a mask to wafers

Contribution of mask line edge roughness (LER) to resist LER on wafers was studied both by simulations and experiments. LER transfer function (LTF) introduced by Naulleau and Gallatin was generalized to include the effect of mask error enhancement factor (MEEF). Low spatial frequency part of LTF was enhanced by MEEF while high spatial frequency part was suppressed due to the numerical aperture limit of a stepper. Our model was experimentally verified as follows. First LER of a mask was measured by a scanning electron microscope. Then the mask LER was multiplied by LTF to simulate the aerial image LER on wafers. It was confirmed that the simulated LER agreed well with the LER measured by AIMSTM. Based on our model the contribution of the mask LER to the resist LER on wafers was estimated. According to our estimation the requirement of the mask LER should be as tight as that of the resist LER on wafers.

Source-Mask co-Optimization (SMO) using Level Set Methods

Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach [3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well. This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also utilizes running on a distributed computing environment. In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect of using different emphasis in defining the cost function will also be studied.

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

Compensation for EUV multilayer defects within arbitrary layouts by absorber pattern modification

According to the ITRS roadmap, mask defects are among the top technical challenges to introduction of extreme ultraviolet (EUV) lithography into production. Making a multilayer defect-free extreme ultraviolet (EUV) blank is not possible today, and is unlikely to happen in the next few years. This means that EUV must work with multilayer defects present on the mask. The method proposed by Luminescent is to compensate effects of multilayer defects on images by modifying the absorber patterns. The effect of a multilayer defect is to distort the images of adjacent absorber patterns. Although the defect cannot be repaired, the images may be restored to their desired targets by changing the absorber patterns. This method was introduced in our paper at BACUS 2010, which described a simple pixel-based compensation algorithm using a fast multilayer model. The fast model made it possible to complete the compensation calculations in seconds, instead of days or weeks required for rigorous Finite Domain Time Difference (FDTD) simulations. In this paper the method is extended from one-dimensional to two-dimensional patterns by formulating the problem with level-set methods. Since only the top layer profile is measurable a multi-layer growth model is applied to infer the location of the defect and how it distorts the multi-layer reflector. The fast image model is applied to determine how these assumptions influence accuracy of the compensation method.

ArF lithography reticle crystal growth contributing factors

The formation of photoinduced crystals and haze has become a challenge for 193nm photolithography high volume manufacturing (1-6). Extensive work has been performed to develop alternative to piranha chemistry for photomask cleaning processes in an attempt to eliminate the incidence of clean induced ammonium sulfate crystal formation (9-13). However, additional factors are impacting 193nm reticle optical quality. Sources of molecular contaminants such as environmental factors, outgasing from pellicle and reticle storage material can generate varieties of photoinduced crystals over the reticle useable lifetime (5-6). This paper will quantify and rank contributing factors for crystals generated under high energy UV exposure. A broad range of analytical and metrology techniques (FTIR, IC, TD-GC/MS, Inorganics impinger, AIMSTM, KLA Starlight, UV 172nm) and improvements in technique sensitivity were developed in order to identify crystal structure, quantify photogenerated contaminants levels and assess wafer printability impact. Engineering systems aimed at minimizing organic and inorganic molecular contaminants levels will be suggested.

Computational metrology and inspection (CMI) in mask inspection, metrology, review, and repair

Abstract Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

Source-mask optimization (SMO): from theory to practice

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Mask Pattern Recovery by Level Set Method based Inverse Inspection Technology (IIT) and its Application on Defect Auto Disposition

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.