David L. Landis

Applications of the IEEE P1149.5 module test and maintenance bus

The proposed IEEE P1149.5 Module Test and Maintenance (MTM) Bus standardizes a serial backplane bus for use in test, diagnosis, and maintenance of electronic subsystems and modules. This paper describes features, capabilities, applications, and current status of the proposed standard; and discusses how P1149.5 can efficiently support low cost testable system designs. Two brief case studies illustrate P1149.5 applications: first as a simple system level gateway to chip level test buses, and second as the core test and maintenance interface for complex, highly reliable systems.

A test methodology for wafer scale system

To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different functional cell types. Details are provided for the function, cell, and wafer level testing standards as well as for the procedures to be followed at wafer level restructuring and test. The test overhead area required is assessed; and for a large class of designs, the benefit of reduced input/output (I/O) area is found to more than compensate for the added test area. >

Wafer-scale optimization using computational availability

It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.<<ETX>>

Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration

Tradeoffs associated with the use of the IEEE 1149.1 serial test interface for wafer-scale-integrated designs are identified. Test circuitry area overhead and yield loss are weighed against the benefits of reduced I/O (input/output) area and improved wafer testability. Where the area overhead of a complete 1149.1 interface is not justifiable for small cells, a simple scan interface which still allows for compliance with the 1149.1 standard at the full wafer system level is proposed. It is shown that the additional test area required may be more than compensated for by the savings in I/O probe pad area. Through a yield analysis driven by the relative areas of the constituent cells, the authors provide a systematic framework for the process of placing 1149.1 test capabilities within a monolithic wafer-scale-system design.<<ETX>>

Test Generation for Precise Interrupts on Out-of-Order Microprocessors

Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions is grossly impractical. This paper describes an enhanced technique for effective verification of a pipelined processor in the event of external interrupts. The paper develops a framework to identify critical points in a test program when resource conflicts and inter-instruction dependencies are large. It is argued that if an external interrupt asserted at the identified points in the test program, then the likelihood of exposing design errors increases.

A wafer scale programmable systolic data processor

The authors describe the programmable systolic data processor (PSDP). The PSDP will enhance US Department of Defense (DoD) mission capabilities by extending signal and data processing speed/performance while reducing system size, weight, and power consumption. The characteristics of this architecture which make it opportune for building as a wafer-scale system include broad homogeneity, ease of redundancy, and limited physical interconnect bandwidth of wafer-scale integration (WSI) using a robust programmable systolic array processing architecture. Thus, it will provide unique onboard processing capabilities for DoD missions.<<ETX>>

Advanced VLSI technologies in biomedical engineering

The microelectronics industry has matured significantly over the past ten years. New very large scale integration (VLSI) technologies are available to researchers and manufacturers which can provide cost effective and innovative solutions to complex problems in biomedical engineering.<<ETX>>

Fault tolerant maintenance networks for highly reliable WSI systems

The application of fault-tolerant network concepts, architectures, and evaluation techniques to dedicated built-in self-test (BIST) maintenance networks (MNets) for wafer scale integration (WSI) systems is described. In particular, the effects on overall WSI system reliability and performance due to wafer level maintenance network interconnection electromigration failures are evaluated. Three novel fault-tolerant MNet architectures are proposed based on loop and bus topologies. The reliability of WSI systems using existing and proposed MNet architectures is determined, and the results illustrate that there are substantial differences in useful system mission lifetimes. In addition, several new performance structures or metrics are proposed. The useful work obtained from these architectures can be grouped into two categories: those which are highly redundant and utilize distributed maintenance processors, and those less redundant architectures which use a single maintenance processor.<<ETX>>

Portable pulse oximetry

P u l s e o x i m e t r y h a s been recommended as a standard of care for every general anesthetic.f.ll The clinical utility of noninvasive pulse oximetry is confirmed daily in operating rooms (ORs), intensive care units (ICUs) and patient wards throughout this country and, indeed, around the world. Portable pulse oximetry offers several major advantages over the currently available systems for present and future health care applications.

Wafer scale integration: a university perspective

This paper presents the Wafer Scale Integration research underway at our university. Specifically, we focus here on theApplications, Architectures, Design, and Test areas. Discussed are the philosophy of such an—admittedly aggressive—effort, the evolving infrastructure for the project, the application-driven architectures developed, and the design and test methodology. The first WSI design is a fully parallel FFT wafer, with application to a high-performance, high-speed CW jamming canceller. Other wafer level designs include an L-U decomposition array, using a newly-developed reciprocal cell, and a multipurpose PE array. The transition from basic tools, such as MAGIC, to commercial tools such as CADENCE, and the importance of a high level description language, VHDL, for modeling and simulation is emphasized. The discipline of reconfiguration, and the associated yield models, incorporating a harvesting factor, are also an integral part of the on-going project. Although, the first wafer will be reconfigured usingLaser linking and Cutting on the in-house laser table, alternative recon-figuration approaches for the other wafer designs are also being considered.