David Malcolm Camm

Temperature diagnostics for a dual-arc FRTP tool

Vorteks new 300 mm flash-assist RTP/spl trade/ tool uses a pair of arc lamps to heat wafers at >200/spl deg/C/s to an intermediate temperature of between 700/spl deg/C and 1200/spl deg/C. A high power, millisecond duration flash is then applied to the device side of the wafer, raising it to a higher peak temperature. Water-cooled windows and the cooling walls of the arcs attenuate incident radiation at the diagnostic wavelength of 1450 nm. This facilitates measuring the temperature of both wafer surfaces during the entire thermal process. A fast radiometer, which samples the back surface of the wafer at 25 kHz, provides feedback to a 1 kHz arc control system. An emissometer measures the back-surface emissivity, while one of its components, a near-infrared camera, provides a two-dimensional map of wafer temperature. An ultra-fast radiometer, which samples at up to 1 MHz, measures the device side of the wafer and estimates the peak temperature of the wafer during the flash. This radiometer has dynamic re-calibration and temperature-compensated electronics. All detectors are InGaAs. The fast radiometer, the ultra-fast radiometer, and the camera have effective resolutions of 16, 14, and 11 bits respectively. The individual components of the temperature measurement system are described. The methodologies used to achieve intermediate temperature control of better than /spl plusmn/2/spl deg/C and emissometer stability of /spl plusmn/0.2% are discussed.

Ultra-shallow junction formation using flash annealing and advanced doping techniques

As the demand for ever shallower, highly active and abrupt junctions continues, it is important to look at both the doping and activation portions of junction formation as a unit process. Advanced doping is useless without annealing methods that limit diffusion and provide high levels of electrical activation and new annealing techniques cannot make the junctions shallower than the as-doped profiles. This work has looked at optimizing several types of advanced doping (Plasma Doping and beamline ion implantation of molecular dopants) and a flash lamp-based ms annealing approach. With this combination, very shallow, abrupt and low resistivity junctions can be formed. Careful characterization was used to ensure the accuracy of the sheet resistance and junction depth measurements.

Emissivity independent process control in a short wavelength arc lamp RTP chamber

Two dimensional temperature measurements of patterned wafers are presented. The measurements are made using a commercially available CCD camera operating at {lambda} = 900nm, yielding a spatial resolution of 1 pixel per mm{sup 2} and a relative accuracy of {+-}0.25 C. The emissivity is determined using a reflectivity measurement made possible by the unique properties of a short wavelength arc lamp RTP chamber. The use of this measurement system for closed loop control is discussed and the application to maintaining accurate time temperature profiles independent of emissivity is described.

Flash thermal processing through the melting point of silicon

The recent capability to achieve sub-millisecond surface temperature increases of greater than 600/spl deg/C over the entire surface of 300 mm wafers using flash-assist rapid thermal processing, fRTP/sup TM/ has allowed the exploration of silicons response to rapid thermal processes over the entire surface of the wafer. Previous results from high-speed processing of silicon through its equilibrium melting point have only been attainable by localized, small area, application of high-powered lasers. We report data obtained from a narrow band radiometer, operating at 1450/spl plusmn/30 nm with a 25 kHz sampling rate, that indicates anomalous emissions during melting. Interesting re-crystallization behavior of the bare silicon surface that is cooling 500.000/spl deg/C/s through its equilibrium melting point after a flash anneal from an intermediate temperature of 900/spl deg/C is also reported. Wafer survivability after exposure to greater than 600/spl deg/C surface temperature jumps from intermediate temperatures of 700/spl deg/C to 900/spl deg/C also demonstrates the inherent robustness of the wafer to withstand large thermal gradient at elevated bulk temperatures imposed during fRTP.

Engineering ultra-shallow junctions using fRTP/sup TM/

This paper discusses engineering of ultra-shallow junctions using a new annealing technique called Flash-assist RTP/sup TM/ (fRTP). This technique offers effective process times in the 1-10 ms range, which fills the gap between traditional RTP and laser thermal processing. A discussion on the evolution of RTP based on the thermal response time of the heat source and wafer is presented. Technical innovations required for fRTP are discussed including why an extremely powerful flash lamp is essential for this application. Comparisons of the various annealing techniques are made and results presented to show the impact on junction depth, abruptness and resistivity. It is shown that a process engineer can more or less independently control diffusion and activation over a wide range enabling the formation of junctions meeting future requirements of the ITRS.

Modeling of a Vortex Water-Wall Argon Arc Lamp for Rapid Thermal Annealing Applications

This paper describes a modeling approach for a vortex water-wall argon arc lamp that is amenable to implementation in real-time controller hardware. The net emission coefficient (NEC) method has been successfully applied for different current levels and can predict the electrical properties of the positive column to sufficient accuracy. The radiation efficiency as a function of the isothermal core temperature has been explained qualitatively, but the correction for radiation efficiency as a function of input power has been implemented as a lookup table using experimental data.

Flash Annealing Technology for USJ: Modeling and Metrology

Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper provides an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details

Determination of Radiative Properties for Water-Wall Plasma Arc Lamp Modeling

Vortex-stabilized water-wall arc lamps are used in rapid thermal processing applications. A key issue is to develop more accurate models so that better control is achieved of the temporal radiation exiting the lamp. The current problem is the lack of a practical means of incorporating radiative transfer. This paper shows that it is possible to obtain a good qualitative understanding of the arc and reasonable quantitative agreement with experiments using the net emission coefficient method to model the isothermal core region of the plasma and a modified version of the mean absorption method to model the surrounding colder regions of the plasma.

Flat-top flash annealing™ for advanced CMOS processing

Millisecond annealing (MSA) has proven to be very helpful for continued scaling of CMOS through its applications in forming highly activated ultra-shallow junctions (USJ) and reducing the thermal budget for nickel silicide contact annealing. As device scaling continues, new materials are being introduced, including high-K dielectrics, metal gates, strained channels and even new channel materials, including Ge and III-V semiconductors. This progress also requires ever-decreasing thermal budget, opening up new opportunities for millisecond annealing. Thermal budget constraints arise from the need to limit atomic diffusion and also to prevent undesirable phase transitions, strain relaxation or defect formation. Limits on the maximum process temperature make it desirable to enable process innovations by extending millisecond annealing beyond the traditional regime of <;1 ms anneal duration. This paper explores how such extended heating profiles can be obtained with the flash-assisted RTP™ technology, where rapid wafer preheating is combined with pulsed surface heating that has a flexible dwell time at the peak temperature, giving the unique ability to perform “soak” anneals in a millisecond time scale. This Flat-Top Flash Annealing™ can help with complex process issues, such as optimization of USJ processes, where there are interactions between dopant activation, diffusion and defect annealing, combined with constraints from device integration requirements. The technology also provides highly uniform and repeatable processing at high wafer throughput, which is essential for high volume manufacturing.