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David R. Stiles

Advanced Micro Devices

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ieee computer society international conference | 1989

Pipeline control for a single cycle VLSI implementation of a complex instruction set computer

David R. Stiles; Harold L. McFarland

A description is given of the pipeline control techniques used in the NexGen processor. This processor implements a complex-instruction-set architecture which supports OS/2 applications. The processor achieves single-cycle execution of most instructions, and has numerous hardware accelerators which minimize pipeline penalties and reduce cycle counts for complex instructions.<<ETX>>

Archive | 1990

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1990

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

John G. Favor; Korbin S. Van Dyke; David R. Stiles

Archive | 1992

Two-level branch prediction cache

David R. Stiles; John G. Favor; Korbin S. Van Dyke

Archive | 2000

Method and apparatus for debugging an integrated circuit

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1995

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1993

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1990

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Korbin S. Van Dyke; David R. Stiles; John G. Favor

Archive | 1990

Integrated single structure branch prediction cache

John G. Favor; David R. Stiles; Korbin S. Van Dyke; Walstein Bennett Smith

Archive | 1996

Branch prediction device with two levels of branch prediction cache

David R. Stiles; John G. Favor; Korbin S. Van Dyke

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John G. Favor

Advanced Micro Devices

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Korbin S. Van Dyke

Advanced Micro Devices

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Harold L. McFarland

Advanced Micro Devices

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Dale R. Greenley

Advanced Micro Devices

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Robert A. Cargnoni

Advanced Micro Devices

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Shrenik Mehta

Advanced Micro Devices

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Teresa A. Roth

Advanced Micro Devices

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Walstein Bennett Smith

Advanced Micro Devices

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