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Korbin S. Van Dyke

Advanced Micro Devices

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Featured researches published by Korbin S. Van Dyke.

Archive | 1990

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1990

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

John G. Favor; Korbin S. Van Dyke; David R. Stiles

Archive | 1992

Two-level branch prediction cache

David R. Stiles; John G. Favor; Korbin S. Van Dyke

Archive | 1993

Configurable branch prediction for a processor performing speculative execution

David L. Puziol; Korbin S. Van Dyke; Larry Widigen; Len Shar; Walstein Bennett Smith

Archive | 2000

Method and apparatus for debugging an integrated circuit

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 2007

Apparatus for executing programs for a first computer architecture on a computer of a second architecture

John S. Yates; Matthew F. Storch; Sandeep Nijhawan; Dale R. Jurich; Korbin S. Van Dyke

Archive | 1995

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1993

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Harold L. McFarland; David R. Stiles; Korbin S. Van Dyke; Shrenik Mehta; John G. Favor; Dale R. Greenley; Robert A. Cargnoni

Archive | 1993

Branch prediction cache with multiple entries for returns having multiple callers

Korbin S. Van Dyke; Larry Widigen; David L. Puziol

Archive | 1990

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Korbin S. Van Dyke; David R. Stiles; John G. Favor

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David R. Stiles

Advanced Micro Devices

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John G. Favor

Advanced Micro Devices

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Stephen C. Purcell

University of Oxford

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Dale R. Greenley

Advanced Micro Devices

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David L. Puziol

Advanced Micro Devices

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Harold L. McFarland

Advanced Micro Devices

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Larry Widigen

Advanced Micro Devices

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Robert A. Cargnoni

Advanced Micro Devices

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Shrenik Mehta

Advanced Micro Devices

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David L. Reese

Sun Microsystems

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