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Featured researches published by David S. Levitan.


ieee computer society international conference | 1995

The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor

David S. Levitan; Thomas Thomas; Paul Kang-Guo Tu

The PowerPC 620 RISC microprocessor is the first chip for the application server and technical workstation product line within the PowerPC family. It utilizes a high performance microarchitecture with many advanced superscalar features to exploit instruction level parallelism. It is the first 64-bit implementation of the PowerPC architecture supporting both 32- and 64-bit application software, and is compatible with the PowerPC 601, PowerPC 603, and PowerPC 604 microprocessors.


Archive | 1993

Method and system for enhanced branch history prediction accuracy in a superscalar processor system

David S. Levitan


Archive | 2003

Method for resource balancing using dispatch flush in a simultaneous multithread processor

William E. Burky; Richard James Eickemeyer; Ronald Nick Kalla; David S. Levitan; Balaram Sinharoy; John Wesley Ward


Archive | 1995

Data processor with programmable levels of speculative instruction fetching and method of operation

Danny K. Jain; David S. Levitan; Paul Charles Rossbach


Archive | 1993

Method and system for single cycle dispatch of multiple instructions in a superscalar processor system

James Allan Kahle; Chin-Cheng Kau; David S. Levitan; Aubrey Deene Ogden; Ali A Poursepanj; Paul Kang-Guo Tu; Donald Emil Waldecker


Archive | 2003

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Gregory W. Alexander; David S. Levitan; Balaram Sinharoy; William J. Starke


Archive | 2010

Hardware Assist for Optimizing Code During Processing

Ronald Hall; Brian R. Konigsburg; David S. Levitan; Brian R. Mestan


Archive | 1993

Method and system for supporting speculative execution of instructions

David S. Levitan


Archive | 2007

System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor

Prabhakar Kudva; David S. Levitan; Balaram Sinharoy; John D. Wellman


Archive | 1994

Method and system for increased instruction dispatch efficiency in a superscalar processor system

James Allan Kahle; Chin-Cheng Kau; David S. Levitan; Aubrey Deene Ogden

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