David Shippy

Introduction to the cell multiprocessor

This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation.

POWER2 fixed-point, data cache, and storage control units

The P0WER2TM fixed-point, data caciie, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an Improved I/O DMA mechanism to support multiple-streaming lUlicro Channels.®

The POWER2 processor

The IBM POWER2 is a second-generation, multi-chip superscalar RISC processor. It provides dual branch processing units, dual fixed-point units, dual floating-point units, and advanced superscalar techniques. It is capable of executing 6 instructions per cycle and 8 operations per cycle. The processor also provides large caches, long cache lines, and high bandwidth buses to memory and I/O.<<ETX>>