James Allan Kahle

Introduction to the cell multiprocessor

This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation.

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end server processor

The next processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.

The Cell Processor Architecture

This talk will present the Cell processor, jointly developed by the STI (Sony-Toshiba-IBM) partnership. Cell is a non-homogeneous chip multiprocessor intended for general-purpose applications but with a particular emphasis on multimedia performance. The Cell processor combines a 64bit Power Architecture(TM) core with 8 Synergistic Processors. In many cases, it delivers more than an order of magnitude more performance than conventional PC processors. Cell achieves this performance and power efficiency improvement by a new division of labor between the Power core and the Synergistic Processors. Cell allows for a wide variety of programming models, a selection of which will be presented in this talk. We will end the talk by discussing some applications that seem to fit the Cell processor particularly well, and by indicating areas of further exploration.

IBM second-generation RISC machine organization

A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously.<<ETX>>

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90 nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption, low-cost design ideal for notebooks and desktop computers.<<ETX>>