David W. Copeland

Low profile heat pipe heat sink and green performance characterization for next generation CPU module thermal designs

Increasing thermal demands of high-end server CPUs require increased performance of air-cooling systems to meet industry needs. Improving the air-cooled heat sink thermal performance is one of the critical areas for increasing the overall air-cooling limit. One of the challenging aspects for improving the heat sink performance is the effective utilization of relatively large air-cooled fin surface areas when heat is being transferred from a relatively small heat source (CPU) with high heat flux. Increased electrical performance for the computer industry has created thermal design challenges due to increased power dissipation from the CPU and due to spatial envelope limitations. Local hot spot heat fluxes within the CPU are exceeding 100 W/cm2, while the maximum junction temperature requirement is 105 C, or less. The CPU power dissipation continues to increase and the number of CPUs per server continues to increase for next generation servers. This has resulted in increased data room energy costs associated with supplying additional power to the server, and also cooling the server. Typically in the past, if two heat sink technologies met the thermal performance requirements along with meeting the reliability performance requirements, the least expensive technology would be utilized. In the future, heat sink thermal performance specifications will consider including the impact of energy cost savings attained through reduced server air flow rate requirements if utilizing a superior heat sink technology warrants a potential increase in heat sink cost.

Thermo-mechanical reliability considerations with dynamic voltage/frequency scaling in microprocessor applications

With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common theme in next-generation CPU offerings will be the use of Dynamic Voltage and Frequency Scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.

A Statistical Approach For Characterizing The Thermal Impact Of TIM Voids

Traditional methods of TIM (thermal interface material) void content specification are often based on a worst case analysis and can often lead to conservative and expensive lid attach design/process development, especially in high performance microprocessor package designs that are the norm today. In a meaningful departure from such methods, we present a practical approach to specify the maximum void content using the methods of statistical analysis. Our approach lends itself to a simple design paradigm where the business side of the package development drives the concept of an acceptable fallout level (AFL) and the technical specifications dictate the acceptable coolable power loss (ACPL). Together, these concepts are tied to a unique void content specification that is significantly less conservative than a worst-case approach, and readily meets the requirements of the design. We illustrate this novel approach for the simple case of TIM voids that have an area-wise uniform probability distribution, and compare the findings with a traditional worst-case void content specification.

Preliminary specification for a closed loop liquid cooling system product reliability test plan

Future high performance systems may incorporate liquid cooling to the board. These systems will be assembled using commercially available components and subsystems, which include the pump, liquid coolant, tubing and connections, heat exchanger, and cold plate. Liquid cooling systems are known to be susceptible to more degradation and failure mechanisms than conventional solid metal heatsinks, heat pipe heatsinks or vapor chamber heatsinks. Component and system providers need guidelines to ensure that their products meet projected reliability requirements. A generic preliminary specification has been assembled based on industry standards and information collected from leading equipment suppliers.

Enabling Dynamic Voltage & Frequency Scaling in next-generation microprocessors: Thermal & reliability considerations

With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common therme in next-generation CPU offerings will be the use of dynamic voltage and frequency. Scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.

On The Correlation Between Multiple Hot Blocks And Package Thermal Resistance

A flip-chip package with square die is considered in this study. Up to four square non-intersecting hot blocks are imposed on the dies otherwise uniform power distribution. Block locations on the die outline are randomly chosen with uniform probability. The power density of a given block is a random parameter, and is permitted to be as high as 10times the baseline uniform bulk power density. Additionally, the size of any block is also treated as a random parameter and is permitted to be as high as 10 % of the die area. A 6000-tuple Monte Carlo study of the packages is conducted, and the package thermal resistance (Rjc) noted in each case. A variety of models are fit to the Rjc using the block characteristics as key variables, and their quality is characterized using the statistical correlation coefficient as a model metric. The results suggest a 96 % correlation between Rjc and the largest product of local power ratio and square of effective local power density ratio among the blocks- providing a simple and useful method to immediately identify blocks with the most impact on Rjc in a die floorplan.