Vadim Gektin

Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling

Thermal design in electronic packaging is driven by the maximum allowable junction temperature of a CPU. An inadequate thermal design that underestimates the junction temperature may adversely impact the electrical performance of the CPU, making predicting the junction temperature a crucial step in package and system thermal design. A numerical model of a heat sink and thermal test package with a uniform and non-uniform power dissipation was created and used to predict their temperatures. The uniform power dissipation case was used to calibrate the numerical models TIM2 thermal impedance. In the non-uniform power cases, the maximum heat flux was over four times higher than the average heat flux. The numerical analysis results in the non-uniform power cases yielded junction temperatures within 2 degrees of the measured values. The heat sink used in the tests as well as numerically modeled contained a vapor chamber base and a plate heat sink. Three different heat sink modeling approaches were used, including: detailed modeling of the heat sink, effective convection coefficient heff, and effective thermal conductivity keff. Test data was used to establish the effective heat transfer coefficient and effective thermal conductivity. A simplified heat sink numerical model allows the computational grid density to be significantly reduced, resulting in fast convergence. Alternate heat sink designs were also considered.

Reliability study of high-end Pb-free CBGA solder joint under various thermal cycling test conditions

This paper described a ceramic ball grid array (CBGA) and its second level reliability. The CBGA uses a substrate with high coefficient of thermal expansion (CTE) and leadfree soldering. The reworkability of the BGA package and board was also studied. The results have shown that this package is reworkable without a significant reliability reduction in the board level reliability. The reliability of solder joints in different chains is monitored and reported separately during the thermal cycling test to understand the impact of the distance to the neutral point. A finite element model of the test setup was created and modeling results were compared with the thermal cycling reliability test data. Acceleration factor has calculated for irregular temperature profiles as compared to the standard ATC profile. The impact of the highest temperature during the temperature cycle as well as the temperature range was shown to follow traditional Norris-Landzbergs equation. A recommendation is made to use the acceleration factor for translating the test data between different temperature cycling scenarios.

Characterizing Bulk Thermal Conductivity and Interface Contact Resistance Effects of Thermal Interface Materials in Electronic Cooling Applications

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material thermal performance during a field operation. Furthermore, a thermal engineer has no a priori knowledge of how large, in addition to the bulk thermal resistance, the interface contact resistances are, and, hence, how much each influences the cooling strategy. In view of these issues, there exists a need for these materials/interfaces to be characterized experimentally through a series of controlled tests before starting on a thermal design. In this study we present one such characterization for a candidate thermal interface material used in an electronic cooling application. In a controlled test environment, package junction-to-case, Rjc, resistance measurements were obtained for various bondline thicknesses (BLTs) of an interface material over a range of die sizes. These measurements were then curve-fitted to obtain numerical models for the measured thermal resistance for a given die size. Based on the BLT and the associated thermal resistance, the bulk thermal conductivity of the TIM and the interface contact resistance were determined, using the approach described in the paper. The results of this study permit sensitivity analyses of BLT and its effect on thermal performance for future applications, and provide the ability to extrapolate the results obtained for the given die size to a different die size. The suggested methodology presents a readily adaptable approach for the characterization of TIMs and interface/contact resistances in the industry.Copyright

Thermal Management of Voids and Delamination in TIMs

The paper parametrically assesses the impact of the voids/delamination on the system thermal performance. Analysis are carried out numerically and validated against experimental data (thermal measurements and C-SAM images). Topics covered include the relationship between voids/delamination and TIMs’ and heat spreader’s effective thermal conductivity; sensitivity of the system thermal performance to void/delamination size and location; voids/delamination impact vs. on the chip power dissipation (uniform vs. non-uniform); comparison of TIM1 vs. TIM2 voids impact; and, finally, comparison of voids vs. delamination.Copyright

Evaluation of high performance thermal greases for CPU package cooling applications

High performance thermal greases have been evaluated in three separate environments: ideal laboratory, in situ laboratory, and system mockup testing to better understand how bulk and interfacial thermal properties, in combination with the test vehicles used, effect the resultant thermal performance. The three methodologies are described and measurements on a baseline material reported.

Evaluation of and Inspection Metrology for Lid Attach for Advanced Thermal Packaging Materials

We have evaluated a new Ag-filled silicone thermal interface material (TIM) for its sensitivity to lid finish and impact on imaging discontinuities in the die/lid (TIM1) layer, in conjunction with two high performance lid materials, as a part of our advanced packaging technology development effort. Thermal and mechanical (shear stress and lid pull) measurements have been carried out on a number of different lid finishes to optimize thermal performance and adhesion at the TIM1/lid interface. This silicone TIM1 is found to be sensitive to the type of Ni-plating and plating bath chemistry. Nondestructive and destructive metrology has been carried out on flip chip (FC) packages using Ag-filled silicone TIM1 and either Cu or AlSiC lids. A number of silicone formulations have been investigated to assess their impact on surface acoustic microscopy (SAM) and X-ray imaging. Nondestructive evaluation (NDE) by real time X-ray and SAM has identified artifacts that make it difficult to unambiguously detect voids and delamination in the TIM1 layer. A “dark ring” or “picture frame” artifact is observed at the die perimeter in acoustic microscope images of packages with the Ag-filled TIM1. Detailed SEM cross-section and thermal mapping analyses on a number of specially constructed FC packages have been correlated with TIM1/lid delamination and voiding observed in SAM and X-ray images. Results of these studies point to changes in the TIM1 modulus during cure and post cure thermal excursions as the cause of the “dark ring” observed in the transmission SAM images rather than delamination at the TIM1/lid or TIM1/die interfaces. However, in the event that delamination is present at the edges it cannot be unambiguously deconvoluted from the “dark ring” artifact in the SAM images.Copyright

Reliability Challenges in Design and Operation of High Heat Powered Processors

Advances in processor design have been made possible in part by increases in the packaging density of electronics. At the same time, combination of increased power dissipation and packaging density has led to substantial growth in the chip and system heat fluxes and amplified complexity in electrical signal integrity and mechanical stack-up design in the recent years, particularly, in the high-end computers. With the trend towards miniaturization, heat removal, along with increased reliability requirements, has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. Cooling of high heat flux components may require consideration of innovative open-loop, as well as plausible closed-loop, cooling designs for data centers. This paper addresses reliability aspects of thermal, electrical, mechanical, and interconnect design and long-life operation of high-end air-cooling, as well as feasible active open and closed-loop cooling technologies of high heat flux processors.Copyright