Davide Appello

High accuracy stimulus generation for A/D converter BIST

A novel approach is presented for digital generation of an analog waveform suitable for BIST of high-resolution analog-to-digital converters (ADCs). The staircase-like exponential waveform is shown to have properties of a perfectly linear ramp when used as the stimulus for a 3rd order polynomial fitting algorithm that measures offset, gain, 2nd and 3rd harmonic distortion. The technique is particularly suitable for testing high resolution (>12 bits) sigma-delta ADCs in a noisy environment, which can then be used to test digital-to-analog converters (DACs). Experimental results for a 44 kHz 16-bit ADC show that the technique measures distortion with better than 0.01% accuracy in the presence of random and 50 or 60 Hz noise.

Understanding yield losses in logic circuits

Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.

System-in-package testing: problems and solutions

System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structure

A P1500 compliant BIST-based approach to embedded RAM diagnosis

This paper deals with the diagnosis of faulty embedded RAMs and outlines the solution which is currently under evaluation within STMicroelectronics. The proposed solution exploits a BIST module implementing a March algorithm, defines a wrapper allowing its interface with a TAP controller, and describes a diagnostic procedure running in the external ATE software environment. The approach allows one to test multiple modules in the same chip through a single TAP interface and is compliant with the proposed P1500 standard for Embedded Core Test. Some preliminary experimental results gathered using a sample circuit are reported, showing the effectiveness of the proposed solution in terms of area and time requirements.

On the automation of the test flow of complex SoCs

Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional nonnegligible effort is required to integrate the test program in an ATE-readable format. In this paper, we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments

Embedded Memory Diagnosis: An Industrial Workflow

Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented

Yield analysis of logic circuits

Complex SOCs developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.

Evaluating Alpha-induced soft errors in embedded microprocessors

This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for different codes implemented as test benchmarks. Test results are then discussed to find the contribution of each available resource to the overall device error rate.

Adapting to adaptive testing

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

A practical evaluation of I/sub DDQ/ test strategies for deep submicron production test application. Experiences and targets from the field

This paper describes work in progress on the development of a test strategy for deep submicron production test application, based on an optimal use of scan, functional and fast I/sub DDQ/ tests. In particular the I/sub DDQ/ part of the DSM production test flow is of interest. In order to compare different strategies as well as the influence of measurement tools, a large number of measurements were carried out on different devices and using different measurement solutions. The results show that in combination with the proper measurement strategy, there is a future for DSM production I/sub DDQ/ testing. Another important conclusion is that the quality of the I/sub DDQ/ measurement equipment is an important factor affecting the screening efficiency.