Vincenzo Tancorre

Understanding yield losses in logic circuits

Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.

On the automation of the test flow of complex SoCs

Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional nonnegligible effort is required to integrate the test program in an ATE-readable format. In this paper, we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments

Embedded Memory Diagnosis: An Industrial Workflow

Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented

Yield analysis of logic circuits

Complex SOCs developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

This paper proposes a new solution for the diagnosis of faults in embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuitry added to the BIST selecting the failure data, and the ATE test program to schedule the data extraction flow. Testing is possible through a standard IEEE 1149.1 TAP, and allows the access to multiple cores with a P1500 compliant solution. The approach aims at implementing a low-cost solution to diagnose embedded RAMs with the goal of minimizing the ATE costs and the time required to extract the diagnostic information. In our approach, the ATE drives the diagnostic scheme and is dedicated to the classification of faults, only, allowing adopting low-cost equipment. The proposed solution allows a scalable extraction of test data, whose amount is proportional to the available testing time. In order to accelerate the fault classification, image processing techniques have been applied The Hough transform has been adopted to analyze the bitmap representing the faulty cells. Preliminary experimental results show the advantages of the proposed approach in terms of time required to complete a diagnostic process.

Enabling Effective Yield Learning through Actual DFM-Closure at the SoC Level

The aim of this paper is to extend the intensive yield learning and manufacturability process further into the process life cycle. This necessarily means employing chips of high circuit complexity, up to the final products complexity. In this way, the actual effects that the design flow will have in combining low-levels of IP can be understood more accurately. The paper will also describe how analysis recipes can be used to isolate different behavior effects and associate them to failure cause. We will also demonstrate techniques which can be adopted in the early ramp-up phase to improve the DFM rules maturity level by progressively fine tuning them with respect to the measured data.

Embedded memory fail analysis for production yield enhancement

The traditional approach for memory fail bitmap analysis is to identify the topological signatures and perform a Failure Analysis investigation on the most frequent signatures, based on the (x, y) coordinates of the fails. This approach is inappropriate when a large portion of the fails are single bits, because too many investigations are required to statistically identify the major repetitive failure mechanisms. This becomes a problem for fast product development and production yield ramp. This paper presents a methodology to classify single fail bits by their unique fault signature, based on the sequence of failing march element read operations from multiple data backgrounds, in a standard Memory BIST flow. These classifications allow investigations to focus on the most important failure mechanisms with greatest yield impact. The methodology is demonstrated in an industrial environment, with identification of critical yield detractors. Starting from a yield problem associated to MBIST failures at high operating temperature, the fault signatures were used to identify a static noise margin parametric problem and a dislocation fault physical problem.

Optimized embedded memory diagnosis

This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.

Rapid root cause analysis and process change validation with design-centric volume diagnostics in production yield enhancement

Identifying systematic failure mechanisms that cause significant yield loss is a primary yield ramp activity. This task is rendered especially difficult for products made with sub-one-hundred nanometer technologies due to the subtle design-process interactions that create transient systematic failure mechanisms. The impact of this difficulty is felt in prolonged ramp cycles and missed market windows for advanced products. A volume diagnostics methodology proposed earlier was seen to resolve this difficulty with highly accurate localization of systematic failures within the design and with an order of magnitude faster time to results compared to traditional approaches. This work presents a few examples of the success of the design-centric volume diagnostics approach in identifying subtle design-process interactions that led to systematic yield loss. It also demonstrates the statistical validation of the process changes introduced to eliminate this yield loss.

Advances on yield learning through concurrent evaluation of design and process data

This paper presents advances in methodologies and tools for yield learning which are concurrently exploiting design, test and process data. In our experiments, we demonstrated how to understand yield losses correlated with excessive power drawn from the chip during functional electrical test of wafers.