Dawon Kahng

A historical perspective on the development of MOS transistors and related devices

T HAS been less than seventeen years since D. Kahng and M. M. Atalla [l] of Bell Telephone Laboratories reported the first demonstration of an Si-Si02 MOS transistor. Even so, the annual sales of MOS based semiconductor components are expected to surpass one billion dollars in the U.S. alone. The impact on our daily lives imparted by these MOS based IC’s is just beginning to be felt. This tremendous explosion has been caused by many innovations and countless numbers of perhaps small but indispensable contributions by many unsung heroes. It is clear then that to list every single landmark, every twist and turn on the road would be just about impossible, even if one had unlimited time to dig into the history and unlimited space in this issue to describe them. It is hoped then that readers will understand that the few milestones related in this article are only those that at the present time the writer feels are more important, without implying completeness or even absolute soundness in his judgment in selecting them. It should also be remarked that what can now be recognized as the more significant milestones did not necessarily stand out and appear so at the times they occurred. Long before the invention of the transistor, the so-called “field. effect,” that is, a conductance change in a solid induced by application of transverse electric field, was the subject of intensive studies by various people. In fact, in the course of these studies, the discovery of transistor action itself was made [2]. As early as the 1920’s and 1930’s, proposals [3], [4] on amplifying devices based on “field effect” were made, however, with little apparent understanding of the physical phenomena. An unequivocal demonstration of the field effect was made by Shockley and Pearson in 1948 in their classic paper [5] in which they showed that an appreciable modulation of conductance in the surface region of a semiconductor occurred. The “field effect“ was subsequently applied to various but essentially similar amplifying device configurations by numerous people. These devices, however, relied on what was recognized as majority (carrier modulation. That is, the transverse electric field caused the majority carrier density to be modulated in a semiconductor bar which in turn resulted in conductance changes between two suitably located ohmic contacts. It is straightforward to show that useful devices based on this principle are achievable only under severe geometrical restrictions. Namely, the ratio

Differential studies of dual‐dielectric charge‐storage cells

By means of novel differential techniques, we have studied the writing and erasing dynamics of DDC cells and, in the process, uncovered a number of unexpected phenomena which play an important role in these processes. For example, we find writing currents qualitatively similar to, but considerably in excess of, those predicted earlier by Fowler‐Nordheim studies on similar MOS structures. We find that these devices can be written with high and undiminished efficiency to 7–10 V of flatband shift depending on insulator thickness, and we determine the limiting source of efficiency degradation beyond these levels. In erase, we find an interesting enhancement due, we believe, to electron‐electron repulsion of the net stored charge. By studying the reversible motion of the stored‐charge centroid at high temperatures, we determine that the effect of the interfacial dopant on the outer insulator extends about 80 A into this layer. Other studies indicate an effect on the thin oxide to be less than 20 A. Low‐field l...

Avalanche punch-through erase (APTE) mode in dual-dielectric charge-storage (DDC) cells

The erase of multilayer charge-storage memory cells by a reverse-bias pulsing of source and drain with the gate and substrate grounded has been previously suggested. Here the physical mechanisms behind this erase mode are explored. It is shown that both punch-through and avalanche are necessary for its operation. This avalanche punch-through erase (APTE) succeeds by pumping majority carriers into a potential pocket at the interface, thereby raising the interface surface potential to a level high enough to allow the stored charge to tunnel out. It is found experimentally that APTE is strongly affected by the lateral leakage of carriers from the pocket. Theoretical curves are presented which show how the pocket itself is affected by the cell geometry, doping level, and pulse amplitude. It appears that APTE is particularly suitable for reprogrammable read-often memories (REPROMs) using dual-dielectric memory cells (DDC/s) with interfacial dopant. These cells allow the use of a gate inhibit voltage pulse which is shown to increase the effectiveness of the APTE, making it a practical approach for random-access REPROM integrated circuits.

A method of tungsten dopant deposition for dual-dielectric charge-storage cells

Electron-beam evaporation of small single-crystal ingots of tungsten has been employed as a laboratory-scale method for introducing the tungsten interfacial dopant in dual-dielectric charge-storage cells. Several other tungsten-evaporation methods, which are potentially more suitable for large-scale manufacturing operations, are evaluated. They are: 1) evaporation from resistively heated tungsten; 2) evaporation of tungsten trioxide powder from a resistively heated crucible; and 3) reactive evaporation of tungsten trioxide from resistively heated tungsten in a low-pressure ambient of oxygen. The latter method, which seemed the most attractive, was tested and was found to be a practical alternative to the electron-beam method. It possesses the advantages of low operating temperatures, control of small deposition rates to produce tungsten trioxide deposits in the submonolayer range of coverage, pure deposits, and requires a minimum of operator attention. Furthermore, sources can have a long operating life.