Louis Carl Parrillo

The reduction of emitter-collector shorts in a high-speed all-implanted bipolar technology

One of the main yield limiting mechanisms in the fabrication of shallow-junction bipolar integrated circuits is emitter-to-collector ( E-C ) leakage. This paper describes the progress made in reducing the E-C leakage defect density in an all-implanted integrated circuit technology, which features emitters approximately 0.5 µm deep and bases approximately 0.3 µm wide. Tile median E-C short density was reduced from approximately 2 × 104to approximately 200/cm2of active emitter area in the course of this study. The processing changes that were adopted to reduce or eliminate the fatal defects include the use of both very low and very high temperature oxidation conditions to eliminate oxidation induced stacking faults (OSFs). A new epitaxial growth technique has reduced the slip dislocation density by more than an order of magnitude. The extended misfit dislocation arrays have been eliminated in both the collector contact and isolation diffusions by reducing the dopant concentrations in each region. Further, dislocation networks arising from buried layer and emitter regions, have been eliminated by limiting the oxygen concentration in their respective drive-in steps.

The sensitivity of transistor gain to processing variations in an all implanted bipolar technology

The integrated circuit technology described here has evolved from one incorporating a transistor with a single base implant providing both the active and inactive base regions of the transistor, to one which employs two separate base implants for each region. The sensitivity of the transistor gain to variations in pertinent processing steps is discussed for each procedure. It is found that the double base implantation procedure provides more flexibility in the tailoring and control of transistor gain.

The reduction of emitter-collector shorts in a high speed, all implanted, bipolar technology

One of the main yield limiting mechanisms in the fabrication of shallow-junction bipolar integrated circuits is emitter-to-collector (E-C) leakage. This paper describes the progress made in reducing theE-Cleakage defect density in an all-implanted integrated circuit technology, which features emitters approximately 0.5 µm deep and bases approximately 0.3 µm wide. Tile medianE-Cshort density was reduced from approximately 2 × 104to approximately 200/cm2of active emitter area in the course of this study. The processing changes that were adopted to reduce or eliminate the fatal defects include the use of both very low and very high temperature oxidation conditions to eliminate oxidation induced stacking faults (OSFs). A new epitaxial growth technique has reduced the slip dislocation density by more than an order of magnitude. The extended misfit dislocation arrays have been eliminated in both the collector contact and isolation diffusions by reducing the dopant concentrations in each region. Further, dislocation networks arising from buried layer and emitter regions, have been eliminated by limiting the oxygen concentration in their respective drive-in steps.