Daying Sun

Analysis and design optimization of brushless DC motor's driving circuit considering the Cdv/dt induced effect

Considering the main parasitic parameters in brushless DC (BLDC) motors driving circuit of “three phase bridge” topology, the switching characteristics under high frequency and large current circumstances are analyzed. Firstly, the switching operation process of the BLDC motors driving circuit is presented. In particular, the Cdv/dt induced effect which is caused by main parasitic parameters of the circuit is analyzed in detail. Secondly, an equivalent circuit of one bridge leg is presented in modeling, and then the analytical solutions of the circuits differential equations are derived. Based on the model, the simulations are performed to study the Cdv/dt induced effect with different values of main parasitic parameters. Finally, several design optimizations of BLDC motors driving circuit are presented, and a practical prototype is used to validate the proposed approach.

A novel digital controller for boost PFC converter with high power factor and fast dynamic response

A novel digital controller for boost power factor correction converter is proposed to achieve high power factor and fast dynamic response. A method of direct duty cycle calculation is adopted to improve the power factor. The prediction module is adopted to estimate the track of the output voltage and the inductor current of next switching cycle in advance to improve the dynamic response. A multiplex successive approximation analog-to-digital converter (ADC) is designed to aim high resolution via little hardware resource. Meanwhile, a novel digital pulse width modulator (DPWM) is realized to improve the regulation linearity. The boost PFC converter with proposed digital controller based on the field programmable gate array (FPGA) has been implemented. Experimental results indicate that the proposed digital controller can achieve high power factor more than 0.98, the dynamic response under load variation is about 80ms and the output voltage overshoot is about 6%.

Low power design for SoC with power management unit

In this paper, motivated by reducing power consumption of system-on-chip (SoC), sets of methods are applied in low power design for SoC, especially power management unit integrated. Corresponding to different applications, different power supply is provided. The whole SoC has been implemented with SMIC 0.13um standard CMOS process, the test results show that the operating frequency is 100MHz and the power consumption is about 96.24 mW.

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

A novel lateral double diffused MOSFET (LDMOS) structure with partial buried-oxide layer under the n-drift region, which is suitable for the bulk silicon epitaxial process, is proposed. The introduction of the buried-oxide layer produces an inversion layer at buried-oxide/p-sub interface and achieves better reduced surface field (RESURF) effect comparing with the conventional device with buried-pwell. Moreover, the buried-oxide can prevent the impurity diffusion and improve the doping concentration of the ndrift region. As a result, the proposed structure improves the breakdown voltage about 12% and increases the current capability over 30% at the same time.