Longxing Shi

High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC

A novel high-voltage (HV) CMOS IC technology using 25-/spl mu/m-thick epitaxy layer based on 1.2-/spl mu/m standard CMOS process for color plasma display panel (PDP) scan-driver ICs has been developed. In this technology, HV n-channel vertical double diffused MOS (nVDMOS), reduced surface field p-channel lateral double diffused MOS (pLDMOS), and the low-voltage CMOS (LVCMOS) are integrated together. The p/sup +/n junction isolation is used to isolate nVDMOS from the pLDMOS, LVCMOS, and other nVDMOSs. A novel level-shift circuit has also been suggested in the PDP scan-driver IC. The experimental results show that the breakdown voltages of the presented nVDMOS and pLDMOS both exceed 200V whether in the OFF or ON state. The rise and fall times of the proposed PDP scan-driver IC are about 270 and 50ns, respectively, which are two important performances to the high response speed of PDPs. The power consumption of the proposed PDP scan-driver IC with the novel level shift circuit has been reduced by about 20% compared with that of the PDP scan-driver IC with the conventional level shift circuit. Furthermore, the cost can be greatly saved using the presented bulk-silicon fabrication technology compared with the silicon-on-insulator technology.

On-Resistance Degradations for Different Stress Conditions in High-Voltage pLEDMOS Transistor With Thick Gate Oxide

The different on-resistance degradations of the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for different hot carrier stress conditions have been experimentally investigated for the first time. The difference results from the interface trap generation and the hot electron injection and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor, which has been analyzed in detail using the MEDICI simulator.

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. To verify the proposed algorithm and architecture, the ADPLL design is implemented by SMIC 0.18-μm 1P6M CMOS technology. The core size of the ADPLL is 582.2 μm * 343 μm. The frequency range of the ADPLL is from 4 to 416 MHz. The measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz. The corresponding power consumption is 11.394 mW.

All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector

A novel all-digital 50% duty cycle corrector (DCC) is pro- posed in this paper. The DCC features include a delay unit based on precharge logic gates with low delay time and a robust SR latch under process voltage and temperature variations for final edge combination over wide frequency and duty-cycle ranges. The rising edge of the output clock has a constant delay when comparing to the input clock, which makes it easy to cooperate with a delay locked loop. The circuit is fabricated in Chartered 0.18-μm CMOS process. The acceptable input clock frequency ranges from 400 MHz to 2 GHz. The correcting error is ±3.5% at 1 GHz or ±1% at 400 MHz.

Further Study of the U-Shaped Channel SOI-LIGBT With Enhanced Current Density for High-Voltage Monolithic ICs

A high-voltage silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) with U-shaped channels, which are composed of parallel channels and orthogonal channels for improving the current density (J_C) and latch-up immunity, is proposed and studied intensively in this paper. By using the U-shaped channels, the electron injection from the emitter into the n-drift region is significantly enhanced, and the current density is improved. In addition, an analytical model is proposed, and it is indicated that J_C can be improved as α (the angle between the parallel channel and the orthogonal channel) increases in a certain range. The hole current density distribution in the ON-state and the lattice temperature distribution in the short-circuit state of the proposed structure are also investigated. Increasing α is beneficial to alleviate the holes crowding beneath the n⁺ emitter and suppress the temperature rise in the JFET region, which is favorable for increasing the latch-up voltage (V_LP) and short-circuit withstand time (t_SC). The experiments demonstrate that the U-shaped channel SOI-LIGBT fabricated with 0.5-μm SOI technology exhibits a high current density (J_C) of 305 A/cm² at V_CE = 3 V and V_GE = 5 V, and a low specific ON-resistance (R_{ON· sp}) of 0.984 Ω · mm² with breakdown voltage of 590 V. The improved latch-up voltage (V_LP) of 560 V and the short-circuit withstand time (t_SC) of 5.1 μs are obtained.

A Novel Silicon-on-Insulator Lateral Insulated-Gate Bipolar Transistor With Dual Trenches for Three-Phase Single Chip Inverter ICs

A silicon-on-insulator lateral insulated gate bipolar transistor with dual trenches located under the high voltage interconnection (HVI), which can be used in 500 V three-phase single chip inverter ICs, is proposed in this letter for the first time. Using the dual trenches to sustain the electric potential from the collector region, the electric field crowding induced by HVI at the silicon surface can be alleviated. The influence of HVI can be shielded completely by adjusting the position and spacing of the trenches. The experimental results show that the breakdown voltage of the proposed structure is 550 V and its latch-up voltage (VLP) at gate-emitter voltage of 15 V (VGE = 15 V) is higher than 500 V. The current density (JC) is 129 A/cm2 when VGE = 5 V and collector-emitter voltage (VCE) is 3 V. The turn OFF time (tOFF) is 132 ns at turn OFF current density of 84 A/cm2.

A high current density SOI-LIGBT with Segmented Trenches in the Anode region for suppressing negative differential resistance regime

A SOI-LIGBT with Segmented Trenches in the Anode region (STA-LIGBT) is proposed and compared with the separated shorted-anode LIGBT (SSA-LIGBT) for the first time. The proposed STA-LIGBT structure features that there are segmented trenches located between the P+ anode and the segmented N+ anodes. By employing the segmented trenches, the resistance between the P+ anode and the shorted N+ anode is significantly increased, which effectively suppresses the negative differential resistance (NDR). The experiments show that the STA-LIGBT with its blocking voltage of 540V can achieve a current density (JC) of 247 A/cm2 when the gate voltage is 10V and the anode voltage is 3V. With the same the NDR regime (the snapback voltage is 1.3V), the current density (JC) of the STA-LIGBT is about 170% of that of the SSA-LIGBT. The fabrication of the segmented trenches is compatible with the trench isolation process and no extra or complicated processes are needed.

The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs.

Electrical Characteristic Study of an SOI-LIGBT With Segmented Trenches in the Anode Region

This paper presents the electrical characteristic of a 500 V silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) with segmented trenches in the anode (STA) region. The STA-LIGBT features segmented n+ anodes and segmented trenches. The segmented n+ anodes are shorted to the p+ anode, which accelerates the extraction of stored electrons during the device turn-OFF. The segmented trenches are arranged between the p+ anode and the shorted n+ anode. The resistors between the adjacent segmented trenches and the adjacent segmented n+ anodes contribute to low snapback voltage (VS) while maintain high current density. In addition, an internal diode is formed by introducing the shorted n+ anode. The 3-D simulations and the experiments are carried out to characterize the electrical performances of the STA-LIGBT and its internal diode. Compared with the conventional SOI-LIGBT, the STA device achieves a 73% improvement in turn-OFF time (tOFF) at the same current density. Correspondingly, the internal diode of the STA-LIGBT achieves a forward voltage drop (VF) of 1.32 V and a reverse recovery time (trr) of 321 ns, which are superior to those of a conventional p-i-n SOI diode.

Temperature-stable voltage reference based on different threshold voltages of NMOS transistors

A temperature-stable voltage reference based on threshold voltages of enhancement and depletion NMOS transistors has been presented and implemented with a 0.5 µm DPDM CMOS technology. The problem of a fixed voltage reference value is avoided by different parameter design. A significant reduce of temperature dependence of mobility is also achieved. The chips area is 0.014 mm2. The test results show that the operation supply voltage is from 2 to 5 V, the maximum supply current is 8.24 µA, and the average reference voltage is 765 mV with an average line regulation of ±0.187%/V. A typical temperature coefficient of 39.2 ppm/°C for a temperature range of 0–100°C is obtained. The power-supply rejection ratio, without any filtering capacitors, is −46 dB at 100 Hz and −32 dB at 1 MHz for the smallest supply voltage.